EPC1LC20N vs EPC1LC20U Comparison
Detailed side-by-side comparison of EPC1LC20N by Intel and EPC1LC20U by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC1LC20N
EPC1LC20N - 1Mb OTP FPGA Configuration PROM | Intel / Altera | PLCC-20
EPC1LC20N NrndSpecification Comparison
| Parameter | EPC1LC20N | EPC1LC20U |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $9.75 |
| Memory Type | OTP Configuration PROM (EPROM-based) | OTP (One-Time-Programmable) Configuration PROM |
| Memory Size | 1 Mbit | β |
| Programmable Type | OTP (One-Time Programmable) | β |
| Configuration Clock Frequency | 16.7 MHz | β |
| Supply Voltage - VCCINT | 4.75 V to 5.25 V | β |
| Supply Voltage - VCCIO | 3.0 V to 3.6 V | β |
| Operating Temperature | 0C to +70C (Commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| Package / Case | 20-LCC (J-Lead), PLCC-20 | β |
| Package Dimensions | 9 mm x 9 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Packaging | Tube | β |
| Configuration Interface | Serial (DATA, DCLK, nCONFIG, nSTATUS) | Altera Serial Configuration (4-wire) |
| Supported FPGA Families | Altera FLEX, APEX, ACEX, Mercury | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (Pb-free finish, "U" suffix) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Memory Density | β | 1 Mbit |
| Maximum DCLK Frequency | β | 8 MHz |
| Package | β | 20-pin PLCC (9x9 mm) |
| Operating Voltage (VCC) | β | 3.3 V typical [DATA_NEEDED: full range] |
| Configuration Time | β | [DATA_NEEDED: depends on bitstream length and DCLK] |
| Cascading Support | β | Yes (multi-PROM daisy-chain for larger bitstreams) |
| Programming Method | β | Altera APU / third-party JTAG programmer |
| Lead-Free (Pb-free) Finish | β | Yes ("U" suffix) |
| Compatibility | β | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) |
| MSL Level | β | [DATA_NEEDED] |