EPC1LC20U - 1Mb FPGA Config PROM, 20-PLCC | Altera
MPN: EPC1LC20U ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPC1LC20U Overview
A configuration PROM is a non-volatile memory that holds the FPGA's bitstream. Because SRAM-based LUT devices (such as the Altera Cyclone, Stratix, and APEX families) lose their configuration when power is removed, the bitstream must be reloaded every time the system powers up. The EPC1LC20U integrates the configuration storage, the serial interface controller, and a precision voltage-reference block in a single package, eliminating the need for external boot memory and reducing board area. In the broader memory hierarchy, the EPC1LC20U sits at the intersection of non-volatile memory (Flash/EPROM/OTP) and FPGA configuration logic.
Key features include 1 Mbit of OTP storage (sufficient for the largest pre-Cyclone-II bitstreams), 8 MHz maximum DCLK rate, open-drain nSTATUS/nCONFIG handshaking, cascading capability to support larger bitstreams through multiple PROMs chained together, and 3.3V typical operation. The 20-pin PLCC package is socket-compatible with the JEDEC-standard 20-PLCC outline, simplifying PCB layout and field programming.
The EPC1LC20U uses Altera's proprietary serial configuration state machine to coordinate with the FPGA. On power-up the FPGA drives nSTATUS low, the PROM presents the bitstream byte-by-byte on DATA, the FPGA clocks it in via DCLK, and signals completion through nCONFIG release. Programming is performed through Altera's Altera Programming Unit (APU) or compatible third-party programmers using JTAG-style pin access.
Typical applications include industrial control FPGA cards, telecom line cards, military/aerospace SRAM-FPGA modules, prototyping boards, and legacy Altera APEX/ACEX/FLEX design support. The OTP architecture makes it suitable for production units where the bitstream is finalized and changes are not expected. When designing with the EPC1LC20U, ensure the JTAG/programming header is accessible and that the nSTATUS/nCONFIG pull-ups are sized correctly (typically 10 kohm to VCC).
Drop-in alternatives for EPC1LC20U — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1LC20U (same form factor and footprint) — differing in Memory Type, Package, Supported FPGA Families, Mounting Type, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LC20N
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EPC144LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.1 / Unit
View Datasheet →EPC1213LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.4 / Unit
View Datasheet →EPC1LC20U Maximum Ratings & Electrical Characteristics
| Memory Type | OTP (One-Time-Programmable) Configuration PROM |
| Memory Density | 1 Mbit |
| Configuration Interface | Altera Serial Configuration (4-wire) |
| Maximum DCLK Frequency | 8 MHz |
| Package | 20-pin PLCC (9x9 mm) |
| Cascading Support | Yes (multi-PROM daisy-chain for larger bitstreams) |
| Programming Method | Altera APU / third-party JTAG programmer |
| Lead-Free (Pb-free) Finish | Yes ("U" suffix) |
| Mounting Type | Surface Mount |
| Compatibility | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) |
| RoHS Status | Compliant (Pb-free finish, "U" suffix) |
EPC1LC20U Pin Configuration
| Pin 1 | DATA — Serial data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nSTATUS — Status signal to FPGA (open-drain) |
| Pin 4 | nCONFIG — Configuration control from FPGA |
| Pin 5 | VCC — Power supply (3.3 V typical) |
| Pin 6 | GND — Ground |
| Pin 7 | NC — Not connected (per datasheet) |
| Pin 8 | NC — Not connected (per datasheet) |
| Pin 9 | NC — Not connected (per datasheet) |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | NC — Not connected (per datasheet) |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | OE — Output enable / nCE (chip enable) |
| Pin 19 | nCS — Chip select |
| Pin 20 | GND — Ground |
Typical Applications
EPC1LC20U is suitable for 6 applications: Legacy Altera FPGA Boot Configuration, Industrial Control FPGA Cards, Telecom Line Card Configuration, Military and Aerospace FPGA Modules, FPGA Development and Prototyping Boards, Production Bitstream Storage for Legacy APEX/FLEX Designs.
Legacy Altera FPGA Boot Configuration
The EPC1LC20U stores and supplies the configuration bitstream to SRAM-based Altera FPGAs in the APEX, FLEX, ACEX, Cyclone (pre-II), and early Stratix families. At power-up the FPGA asserts nCONFIG/nSTATUS, the EPC1LC20U presents the bitstream serially on DATA at up to 8 MHz DCLK, and configuration completes without external Flash. The 1-Mbit density is sufficient for the largest pre-Cyclone-II bitstreams; for smaller designs the EPC144LC20 or EPC1213LC20 in the same 20-PLCC footprint offer the same interface at lower cost. Place a 10 kohm pull-up on nSTATUS and nCONFIG to VCC and keep DATA/DCLK traces short to avoid skew.
Recommended
Industrial Control FPGA Cards
Industrial PLC and motion-control boards that use Altera FPGAs for high-speed I/O and deterministic logic rely on the EPC1LC20U for non-volatile boot storage. The OTP architecture guarantees that the bitstream cannot be altered by field reprogramming - desirable for safety-certified or IP-locked industrial designs. The 20-PLCC package supports both SMT and socketed assembly, simplifying field service and rework. Designers benefit from Altera's Quartus-II toolchain integration and from the 8 MHz passive-serial interface that requires only four FPGA pins (DCLK, DATA, nSTATUS, nCONFIG), freeing more I/O for application use.
Recommended
Telecom Line Card Configuration
Telecom line cards and base-station subsystems built on Altera FPGAs use the EPC1LC20U as the central boot source. The PROM's 1-Mbit density supports multi-protocol bitstreams, and the cascading interface allows designers to chain a second EPC1LC20U to extend storage for large Stratix-class designs. The 8 MHz DCLK rate yields configuration times around 130 ms for a full 1-Mbit bitstream, fast enough for telecom power-rail sequencing requirements. Lead-free (U-suffix) finish supports RoHS telecom builds shipping into EU and APAC markets.
Recommended
Military and Aerospace FPGA Modules
Defense and aerospace subsystems using extended-temperature Altera FPGAs require rugged, non-volatile boot memory, and the EPC1LC20U in 20-PLCC meets that need. Its OTP architecture is well suited to bitstreams that are frozen at production and must not be modified in the field - a common requirement for DO-254 and MIL-HDBK-454 compliance. Designers pair the PROM with a mil-spec FPGA (e.g., APEX or ACEX ruggedized versions) on conduction-cooled boards. The 20-PLCC through-hole-style footprint also tolerates mechanical stress and thermal cycling better than finer-pitch SOIC alternatives.
Recommended
FPGA Development and Prototyping Boards
University labs, evaluation kits, and reference designs targeting legacy Altera FPGAs use the EPC1LC20U as the default boot source. The PLCC socket allows students and engineers to swap bitstreams by re-programming a fresh PROM, supporting multiple design iterations without board rework. The 8 MHz passive-serial interface is straightforward to drive from soft logic in the FPGA itself, useful for lab demos of self-configuration or cascaded-PROM boot sequences. Pair the EPC1LC20U with a Quartus-II reference design to walk through the full compile/program/verify cycle in a classroom setting.
Recommended
Production Bitstream Storage for Legacy APEX/FLEX Designs
Long-lifecycle production systems that use APEX 20K, FLEX 10K, or ACEX 1K FPGAs rely on the EPC1LC20U to store the finalized bitstream permanently. Because these designs often ship for 15-20 years, sourcing the same configuration PROM across the program lifetime is critical. The OTP-only architecture prevents accidental field overwrites that could brick deployed units, and the Altera-standard 20-PLCC footprint is interchangeable with multiple second-source suppliers listed in the cross-reference. Designers maintain a long-term inventory agreement with authorized distributors to secure supply through end-of-life.
Recommended
Recommended Products Summary
Engineering reference data for EPC1LC20U — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1LC20 | EPC1LC20N | EPC144LC20 | EPC1213LC20 |
|---|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera | Altera | Altera | Altera |
| Package | 20-pin PLCC (9x9 mm) | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same |
| Memory Type | OTP | OTP | OTP | OTP | OTP |
| Configuration Interface | Altera 4-wire passive serial | Altera 4-wire passive serial | Altera 4-wire passive serial | Altera 4-wire passive serial | Altera 4-wire passive serial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lead-free Pb-free finish on a proven legacy Altera design (vs EPC1LC20)
- 1-Mbit density sufficient for the largest pre-Cyclone-II bitstreams (vs EPC144LC20)
- Same PLCC footprint across the Altera EPC family (vs EPCS1 / EPCQ1)
- Cascading capability for very large bitstreams (vs EPC144LC20)
Design Notes
Use 10 kohm pull-up resistors on nSTATUS and nCONFIG to VCC (typically 3.3 V). Place these resistors as close as possible to the FPGA pins, not the PROM, to ensure clean edges during configuration handshaking. Add a 0.1 uF decoupling capacitor directly between the EPC1LC20U VCC and GND pins, and a 1 uF bulk capacitor nearby to handle inrush current during configuration.
Keep the DCLK and DATA traces between the EPC1LC20U and the FPGA short and length-matched within ~25 mm to minimize skew. Route them away from switching power converters and high-speed data lines; the configuration interface is sensitive to crosstalk at the 8 MHz DCLK edge. For multi-PROM cascading, place the secondary EPC1LC20U within 50 mm of the primary and daisy-chain nCASC/next-DATA lines per the Altera datasheet.
Do not confuse the EPC1LC20U (20-PLCC, 4-wire passive serial) with the EPCS1/EPCQ1 (8-SOIC, active serial SPI). They share the 1-Mbit density but use completely different pinouts and configuration protocols - the EPCS1/EPCQ1 cannot be a drop-in replacement on the same footprint. Also confirm the FPGA target family: passive-serial 4-wire EPC PROMs work with APEX, FLEX, ACEX, Cyclone (pre-II), and early Stratix, but Cyclone III/IV/V and Stratix III/IV/V/10 require EPCQ-series active-serial devices.
The EPC1LC20U operates from a single 3.3 V typical supply (consult the datasheet for the full VCC tolerance window). During configuration the PROM may draw brief inrush current of several mA as internal counters cycle - ensure the 3.3 V rail has at least 50 mA of headroom beyond quiescent load. For battery-backed or power-sequenced designs, hold the FPGA in reset (nCONFIG low) until VCC is stable for at least 1 ms before releasing.
Compliance Information
Pb-free finish indicated by "U" suffix per Altera naming convention. Other compliance data (REACH, halogen, conflict minerals) not published for this legacy part; consult the latest Intel FPGA compliance statements if required.
