EPC1LI20 vs EPC2LC20 Comparison

Detailed side-by-side comparison of EPC1LI20 by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1LI20 EPC2LC20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $8.50 $7.20
Memory Type OTP Configuration PROM (EPROM-based) Non-volatile configuration PROM
Memory Size 1 Mb (1,048,576 bits) 1.6 Mbit
Configuration Interface Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Maximum Configuration Clock 8 MHz β€”
Supply Voltage (VCC) 5.0 V (4.75 V to 5.25 V) β€”
Programming Voltage (VPP) 12.75 V (typical, factory-programmed via JTAG) β€”
Package 20-pin PLCC (J-lead, 9x9 mm) 20-pin PLCC (J-lead, 9x9 mm)
Pin Count 20 β€”
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Cascading Support Yes (nCASC pin for multi-device daisy chain) β€”
Endurance OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) β€”
JTAG Programming Yes (in-system via IEEE 1149.1) β€”
Compatible FPGA Families FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
MSL Level 1 (per Partstack datasheet record) β€”
RoHS Status [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] Non-Compliant (original Altera Pb-containing part)
Programming Interface β€” IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC β€” 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range β€” 5.0 V or 3.3 V
Supported FPGA Families β€” ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Cascade Support β€” Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Lead-Free Version β€” EPC2LC20N available as lead-free equivalent
Programming Support β€” Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan β€” IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Datasheets & Resources

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