EPC2LC20-V vs EPC2LC20 Comparison

Detailed side-by-side comparison of EPC2LC20-V by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC2LC20-V

EPC2LC20-V - 1.6Mb FPGA Config PROM, 20-PLCC | Altera

EPC2LC20-V Obsolete

Specification Comparison

Parameter EPC2LC20-V EPC2LC20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.45 $7.20
Memory Type Configuration PROM (Flash-based, in-system programmable) Non-volatile configuration PROM
Memory Density 1.6 Mbit β€”
Configuration Interface Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Maximum Configuration Clock 10 MHz β€”
Supply Voltage VCC 3.3 V 3.0 V to 3.6 V (3.3-V operation)
I/O Tolerance 5 V tolerant on configuration pins β€”
In-System Programming Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) β€”
Cascade Support Yes, daisy-chainable for >1.6 Mbit designs Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Operating Temperature Range (V suffix) 0 Β°C to +70 Β°C (commercial) β€”
Package Type 20-pin PLCC (JEDEC MS-018) β€”
Package Dimensions 9 x 9 mm body, 1.27 mm pitch β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
RoHS Status Compliant (per distributor listings) Non-Compliant (original Altera Pb-containing part)
Lead-Free Yes β€”
Memory Size β€” 1.6 Mbit
Programming Interface β€” IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
ISP Voltage Range β€” 5.0 V or 3.3 V
Package β€” 20-pin PLCC (J-lead, 9x9 mm)
Operating Temperature β€” -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Lead-Free Version β€” EPC2LC20N available as lead-free equivalent
Programming Support β€” Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan β€” IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Datasheets & Resources

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