EPC2LC20-V - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
MPN: EPC2LC20-V ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.95 | $129.50 |
| 100 | $11.4 | $1,140.00 |
| 500 | $10.2 | $5,100.00 |
| 1,000 | $9.45 | $9,450.00 |
EPC2LC20-V Overview
A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and loads it into the SRAM-based LUT device at power-up, reset, or upon reconfiguration request. Within the broader hierarchy, configuration PROMs sit at the boot-memory layer beneath FPGAs and CPLDs, between power-on reset events and the user logic — EPC1/EPC2 series parts specifically support Altera (now Intel) APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, and MAX 9000 device families, simplifying single-chip configuration and enabling remote in-system reconfiguration via JTAG.
Key features include 1.6 Mbit of Flash-based configuration storage, a serial configuration interface clocked up to 10 MHz, in-system programmability through the IEEE 1149.1 (JTAG) boundary-scan port, and a cascadable daisy-chain interface that allows multiple EPC2 devices to be linked for designs exceeding the single-device capacity. The -V suffix indicates the commercial operating temperature range of 0 °C to +70 °C, while the LC family provides the low-cost tier of the EPC2 line.
Technically, the EPC2LC20-V uses a 3.3 V core supply (VCC) with 5 V-tolerant I/O on configuration interface pins, four JTAG pins (TMS, TCK, TDI, TDO) supporting boundary-scan and ISP, and dedicated nCS, nSTATUS, CONF_DONE, and DCLK pins for the FPGA configuration handshake. The 20-pin PLCC package (JEDEC MS-018) provides a socket-friendly footprint suitable for prototyping sockets, field upgrades, and legacy replacement scenarios.
Typical applications include configuring APEX 20K and ACEX 1K FPGA prototype boards, industrial control systems with field-upgradable logic, telecommunications line cards using FLEX 10K devices, and military/aerospace ground-test fixtures built around MAX 9000 parts. The 1.6 Mbit density is dimensioned for mid-density APEX 20K designs and most ACEX 1K configurations.
Designers should budget for the dedicated JTAG header and ensure that the PROM-to-FPGA DCLK/nSTATUS/CONF_DONE handshake traces are kept short. For multi-PROM cascading, ensure that the cascaded chain does not exceed the FPGA's maximum configuration clock frequency or supported PROM count.
This page consolidates distributor pricing, drop-in alternatives in the same 20-PLCC footprint, and practical design considerations not directly summarized in the Altera configuration-device datasheet — distinct information gain relative to manufacturer PDF and Octopart listings.
Drop-in alternatives for EPC2LC20-V — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20-V (same form factor and footprint) — differing in Memory Type, Cascade Support, Configuration Interface, Package, Supported FPGA Families.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LI20N
✅ Drop-In✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LI20
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20-U
✅ Drop-In✓ In Stock
$9.6 / Unit
View Datasheet →EPC2LC20-T
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LC20-V Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration PROM (Flash-based, in-system programmable) |
| Memory Density | 1.6 Mbit |
| Configuration Interface | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) |
| Maximum Configuration Clock | 10 MHz |
| Supply Voltage VCC | 3.3 V |
| I/O Tolerance | 5 V tolerant on configuration pins |
| In-System Programming | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) |
| Cascade Support | Yes, daisy-chainable for >1.6 Mbit designs |
| Operating Temperature Range (V suffix) | 0 °C to +70 °C (commercial) |
| Package Type | 20-pin PLCC (JEDEC MS-018) |
| Package Dimensions | 9 x 9 mm body, 1.27 mm pitch |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 |
| RoHS Status | Compliant (per distributor listings) |
| Lead-Free | Yes |
EPC2LC20-V Pin Configuration
| Pin 1 | TDI — JTAG Test Data In |
| Pin 2 | TMS — JTAG Test Mode Select |
| Pin 3 | TCK — JTAG Test Clock |
| Pin 4 | nCS — Chip Select (active low) |
| Pin 5 | VCC — 3.3 V core supply |
| Pin 6 | DCLK — Configuration clock to FPGA |
| Pin 7 | DATA — Configuration data output to FPGA |
| Pin 8 | nINIT_CONF — Initiate configuration (active low) |
| Pin 9 | GND — Ground |
| Pin 10 | nSTATUS — Configuration status (active low) |
| Pin 11 | CONF_DONE — Configuration complete indicator |
| Pin 12 | OE — Output enable for DATA pin |
| Pin 13 | nCASC — Cascade output to next EPC2 device (active low) |
| Pin 14 | LED_CASC — Cascade activity LED driver |
| Pin 15 | TDO — JTAG Test Data Out |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | NC — Not connected (per datasheet) |
Typical Applications
EPC2LC20-V is suitable for 7 applications: APEX 20K FPGA Configuration, ACEX 1K Prototyping Boards, FLEX 10K Industrial Control, Telecommunications Line Cards, MAX 9000 CPLD Configuration Support, Legacy Avionics Ground-Test Fixtures, FPGA Education and University Labs.
APEX 20K FPGA Configuration
The EPC2LC20-V's 1.6 Mbit density is dimensioned for mid-density APEX 20K designs, storing the full configuration bitstream and loading it through the Altera serial configuration interface at up to 10 MHz. The JTAG ISP enables remote in-system upgrades without removing the board, ideal for industrial APEX-based designs. Place the PROM in the same 20-pin PLCC socket adjacent to the APEX 20K device; route DCLK, nSTATUS, and CONF_DONE as short, impedance-controlled traces to meet the configuration-clock skew budget.
Recommended
ACEX 1K Prototyping Boards
ACEX 1K FPGAs in the EP1K10, EP1K30, and EP1K50 densities fit comfortably within the EPC2LC20-V's 1.6 Mbit capacity, making this PROM a standard companion part for ACEX-based development kits. The in-system programmability simplifies prototype iteration: engineers can reflash the bitstream over JTAG without swapping UV-erasable PROMs. Use the EPC2 cascade chain when targeting larger ACEX designs that exceed 1.6 Mbit. The 20-pin PLCC package also accepts low-cost production sockets.
Recommended
FLEX 10K Industrial Control
FLEX 10K designs in factory automation, motor control, and process instrumentation often use the EPC2LC20-V as the configuration memory because its commercial temperature grade suits indoor control cabinets. The 5 V-tolerant configuration I/O allows direct connection to legacy 5 V FLEX 10K parts without level shifters, and the JTAG ISP supports field firmware updates through the same JTAG header used for boundary-scan production test. Cascade multiple EPC2 devices when the FLEX 10K bitstream exceeds 1.6 Mbit.
Recommended
Telecommunications Line Cards
Telecom line cards based on FLEX 10K or APEX 20K FPGAs use the EPC2LC20-V to enable remote in-system reconfiguration for protocol upgrades and field fixes — a critical capability when line cards must be upgraded without service interruption. The JTAG ISP interface can be tied to the card's management microcontroller, allowing remote bitstream updates over the backplane. The commercial 0-70 °C operating range matches central-office and customer-premises equipment thermal envelopes, and the 20-pin PLCC socket allows fast field replacement.
Recommended
MAX 9000 CPLD Configuration Support
Although MAX 9000 CPLDs typically configure from a parallel EPROM, designs that pair a MAX 9000 device with a larger FPGA on the same board can use the EPC2LC20-V as a consolidation point: the EPC2 cascade chain delivers both bitstreams through a single daisy-chain. This reduces board area and BOM cost versus using two separate configuration memories. The JTAG ISP allows the MAX 9000 glue-logic bitstream to be updated alongside the FPGA bitstream over a single JTAG header.
Recommended
Legacy Avionics Ground-Test Fixtures
Avionics ground-test fixtures and lab emulators built around APEX 20K and ACEX 1K FPGAs use the EPC2LC20-V in socketed 20-pin PLCC carriers so test-program bitstreams can be swapped quickly between test runs. The socket-friendly package minimizes fixture downtime during bitstream changeovers, and the JTAG ISP allows in-fixture reprogramming without removing the PROM. Although the EPC2LC20-V is commercial grade, ground-test fixtures in climate-controlled labs operate well within the 0-70 °C envelope.
Recommended
FPGA Education and University Labs
University FPGA labs and Altera/Intel training kits rely on the EPC2LC20-V to provide plug-and-play configuration for APEX 20K and ACEX 1K development boards, because students can quickly swap the 20-pin PLCC PROM to test alternative bitstreams without JTAG programmers. The in-system programmable Flash allows instructors to pre-load multiple reference designs and let students reprogram the PROM via JTAG during lab sessions. The PLCC socket also tolerates repeated insertion cycles typical of classroom use.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20-V — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LI20N | EPC2LI20 | EPC2LC20 | EPC2LC20-U | EPC2LC20-T |
|---|---|---|---|---|---|---|
| Package | 20-PLCC | 20-PLCC (same footprint) | 20-PLCC (same footprint) | 20-PLCC (same footprint) | 20-PLCC (same footprint) | 20-PLCC (same footprint) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit |
| Max Configuration Clock | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| In-System Programming (JTAG) | Yes | Yes | Yes | Yes | Yes | Yes |
| Cascade Support | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Commercial-grade temperature rating at -V tier (vs EPC2LI20N)
- Drop-in compatible with full EPC2 family in 20-PLCC (vs EPC2LC20 (base variant))
- In-system programmable Flash vs one-time-programmable PROMs (vs Legacy Altera EPC1 PC8/PI8 series)
Design Notes
Estimated: The EPC2LC20-V is factory-obsolete as of 2026-09-11; do not use it for new designs without an obsolescence mitigation plan. For new APEX 20K or ACEX 1K designs that must use the EPC2 architecture, select the EPC2LI20N (industrial grade, Pb-free) as the primary drop-in, with the EPC2LC20 as a secondary source. Long-term, migrate the FPGA to a Cyclone, Arria, or Stratix family and use commodity SPI flash — these newer Intel FPGAs do not support the EPC2 PROM interface at all.
Route the EPC2LC20-V DCLK, nSTATUS, CONF_DONE, and DATA traces as short, impedance-matched lines directly to the target FPGA. The Altera configuration handshake is sensitive to DCLK skew — keep the DCLK trace under 50 mm if possible and avoid routing it parallel to switching signals. Place the 20-pin PLCC socket or land pattern so the chamfered corner (pin 1 indicator) is unambiguous; pin 1 is TDI per the Altera datasheet pinout. Decouple VCC (pin 5) with a 0.1 µF ceramic capacitor placed within 3 mm of the pin.
When cascading multiple EPC2 devices, wire nCASC (pin 13) of the upstream device to nCS (pin 4) of the downstream device, and chain the DATA outputs in series. The Altera datasheet allows up to 4 EPC2 devices in a cascade chain for designs up to 6.4 Mbit, but verify against the target FPGA's maximum supported PROM count. Add a 10 kΩ pull-up on nSTATUS and CONF_DONE to VCC if the FPGA does not provide internal pull-ups. Use the JTAG chain (TDI/TMS/TCK/TDO) for ISP, including in-system cascade reprogramming.
The EPC2LC20-V operates from a single 3.3 V VCC supply (pin 5) with 5 V-tolerant I/O on configuration pins. Estimated: typical ICC during configuration is below 50 mA, but inrush during initial Flash read can spike — bulk-decouple VCC with a 10 µF tantalum or ceramic capacitor near the package. Confirm the 3.3 V rail is stable before nSTATUS is released; power-rail glitches during configuration can corrupt the bitstream load. The device draws negligible standby current once configuration completes, so no special power-down sequencing is required.
Compliance Information
RoHS and REACH compliance per distributor listings (DigiKey, Mouser). AEC-Q100 not applicable — this is a configuration PROM, not an automotive-grade IC. Halogen-free status not stated explicitly in verified data.
