EPC2LC20-V vs EPC2LI20 Comparison

Detailed side-by-side comparison of EPC2LC20-V by Altera and EPC2LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC2LC20-V

EPC2LC20-V - 1.6Mb FPGA Config PROM, 20-PLCC | Altera

EPC2LC20-V Obsolete

Specification Comparison

Parameter EPC2LC20-V EPC2LI20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.45 $5.95
Memory Type Configuration PROM (Flash-based, in-system programmable) Flash (in-system programmable)
Memory Density 1.6 Mbit β€”
Configuration Interface Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) Serial or Byte-wide (parallel)
Maximum Configuration Clock 10 MHz β€”
Supply Voltage VCC 3.3 V β€”
I/O Tolerance 5 V tolerant on configuration pins β€”
In-System Programming Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) β€”
Cascade Support Yes, daisy-chainable for >1.6 Mbit designs β€”
Operating Temperature Range (V suffix) 0 Β°C to +70 Β°C (commercial) β€”
Package Type 20-pin PLCC (JEDEC MS-018) β€”
Package Dimensions 9 x 9 mm body, 1.27 mm pitch β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket-compatible)
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 β€”
RoHS Status Compliant (per distributor listings) [DATA_NEEDED: RoHS status]
Lead-Free Yes β€”
Memory Size β€” 1.6 Mb (1,572,864 bits)
Programmable Type β€” In System Programmable (ISP)
Function β€” Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating β€” 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
Operating Temperature β€” -40 C to +85 C (Industrial)
Package / Case β€” 20-PLCC (J-lead, 9x9 mm)
Decompression β€” On-chip (supports compressed bitstreams)
JTAG / ISP Interface β€” IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support β€” Yes (daisy-chain configuration)
User-Accessible Memory β€” Yes (unused flash available to user logic)
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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