EPC2LI20 - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
MPN: EPC2LI20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.92 | $89.20 |
| 100 | $7.75 | $775.00 |
| 500 | $6.8 | $3,400.00 |
| 1,000 | $5.95 | $5,950.00 |
EPC2LI20 Overview
What is a configuration PROM? A configuration PROM (Programmable Read-Only Memory) is a non-volatile memory device that holds the FPGA's configuration bitstream and reloads it into the SRAM-based LUT fabric every time the system powers up, initializes, or needs new configuration data. Because SRAM FPGAs lose their logic configuration when power is removed, they require an external boot memory source; configuration PROMs sit at the bottom of the programmable-logic memory hierarchy (PROM -> volatile configuration memory -> FPGA logic fabric) and remain the simplest drop-in boot-source solution for legacy Altera/Intel FPGA designs.
The EPC2 device family combines a flash memory array with an internal controller that handles the serial or parallel configuration interface to one or more Altera FPGAs. Key features include in-system programmability via IEEE 1532 JTAG, on-chip voltage-sensing circuitry that automatically selects 3.3V or 5.0V operation, support for both serial and parallel (byte-wide) configuration modes, and a programmable decompression engine that lets compressed bitstreams occupy as little as 35% of the equivalent uncompressed image. The flash also offers user-accessible memory space that can be used by a Nios embedded processor or external PLD for general-purpose non-volatile storage.
In typical designs the EPC2LI20 connects directly to the FPGA's DATA, DCLK, nCONFIG, nSTATUS, and CONF_DONE pins, with JTAG signals (TCK, TMS, TDI, TDO) brought out for in-system programming. The controller sequences the configuration automatically after POR, monitors nSTATUS, and can chain-load additional FPGAs in a multi-device configuration chain. Because configuration is read out of flash serially or by byte, the EPC2LI20 supports both legacy FPGAs and Altera's MAX II, Cyclone, Stratix, and APEX device families.
Common applications include industrial control boards, factory automation equipment, telecom line cards, and legacy FPGA-based test platforms that need a compact through-hole boot memory. Choose EPC2LI20 when the design uses a PLCC-20 footprint and must operate from -40C to +85C; choose EPCQ or EPCQ-A configuration devices for new designs where Intel/Altera recommends migrating from EPC2-series PROMs.
When designing with the EPC2LI20, route JTAG signals as a star from a single header so that the chain can be re-programmed in-system without disturbing other board-level signals. Place a 0.1 uF decoupling capacitor as close as practical to the VCC and VPP pins, and verify that nCONFIG and nSTATUS are pulled to the correct logic level through 10 kohm resistors. The PLCC-20 footprint accommodates both socketed and direct-solder mounting; sockets are preferred for production programming.
This page synthesizes distributor pricing, drop-in alternatives sourced from the Altera/Intel cross-reference data, and practical design notes that complement the manufacturer datasheet.
Drop-in alternatives for EPC2LI20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LI20 (same form factor and footprint) β differing in Memory Type, Package, Memory Size, Cascade Support, Interface.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC2LC20N
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC2LC20
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPC2LI20N
β Drop-Inβ In Stock
$5.1 / Unit
View Datasheet βEPC20LI20N
β Drop-Inβ In Stock
$17.5 / Unit
View Datasheet βEPC1LI20
β Drop-Inβ In Stock
$8.5 / Unit
View Datasheet βEPC2LI20 Maximum Ratings & Electrical Characteristics
| Memory Size | 1.6 Mb (1,572,864 bits) |
| Memory Type | Flash (in-system programmable) |
| Programmable Type | In System Programmable (ISP) |
| Function | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Package / Case | 20-PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount (PLCC socket-compatible) |
| Configuration Interface | Serial or Byte-wide (parallel) |
| Decompression | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | Yes (daisy-chain configuration) |
| User-Accessible Memory | Yes (unused flash available to user logic) |
EPC2LI20 Pin Configuration
| Pin 1 | DATA β Configuration data output to FPGA |
| Pin 2 | DCLK β Configuration clock input from FPGA |
| Pin 3 | VCC β Power supply (3.3V or 5.0V) |
| Pin 4 | nCONFIG β Configuration control input (active low) |
| Pin 5 | nSTATUS β Status output to FPGA (active low) |
| Pin 6 | CONF_DONE β Configuration-done output |
| Pin 7 | TDI β JTAG test data in |
| Pin 8 | TMS β JTAG test mode select |
| Pin 9 | TCK β JTAG test clock |
| Pin 10 | GND β Ground |
| Pin 11 | TDO β JTAG test data out |
| Pin 12 | VPP β Programming voltage supply (per datasheet) |
| Pin 13 | NC β Not connected (per datasheet) |
| Pin 14 | NC β Not connected (per datasheet) |
| Pin 15 | NC β Not connected (per datasheet) |
| Pin 16 | NC β Not connected (per datasheet) |
| Pin 17 | OE β Output enable (per datasheet) |
| Pin 18 | nCS β Chip select (per datasheet) |
| Pin 19 | NC β Not connected (per datasheet) |
| Pin 20 | GND β Ground |
Typical Applications
EPC2LI20 is suitable for 6 applications: Legacy Altera FPGA Configuration Boot Memory, Industrial Control and Factory Automation, Telecommunications Line Cards and Backplane Controllers, Test and Measurement Instrumentation, Multi-FPGA Daisy-Chain Configuration, User Non-Volatile Memory for Nios II / PLD Systems.
Legacy Altera FPGA Configuration Boot Memory
The EPC2LI20 is purpose-built to load the configuration bitstream into SRAM-based Altera FPGAs such as APEX, ACEX, Cyclone, Stratix, and MAX II at every power-up. Its 1.6 Mb of flash comfortably stores an uncompressed configuration image for mid-density Altera devices, while on-chip decompression shrinks large bitstreams to roughly 35% of their uncompressed size - so a single EPC2LI20 can boot many modern FPGAs even when the raw image exceeds 1.6 Mb. Connected to the FPGA's DATA/DCLK/nCONFIG/nSTATUS/CONF_DONE pins with JTAG brought out for ISP, the device offers proven, drop-in boot storage for industrial control, telecom, and test-and-measurement boards.
Recommended
Industrial Control and Factory Automation
Programmable logic controllers (PLCs), motor drives, and human-machine interface (HMI) panels often rely on Altera Cyclone or MAX series FPGAs paired with the EPC2LI20 for deterministic boot from a -40 C to +85 C industrial-temperature configuration source. The PLCC-20 socketed package supports field replacement of boot memory, which simplifies field service for installed industrial systems. With 3.3V/5.0V auto-sensing, the EPC2LI20 powers directly from common 5V or 3.3V industrial rails without external level shifters, lowering BOM cost in long-life factory automation equipment.
Recommended
Telecommunications Line Cards and Backplane Controllers
Legacy telecom line cards frequently use Altera FPGAs as glue logic between PHYs, TDM buses, and backplane SERDES, with the EPC2LI20 supplying the boot bitstream on a PLCC-20 socketed footprint. Its 3.3V/5.0V dual supply and on-chip decompression let one part boot multiple FPGAs in daisy-chain configuration, while the 1.6 Mb flash can hold compressed images for large Stratix-class devices. For telecom-grade reliability, the industrial -40 C to +85 C rating ensures operation across central-office and outside-plant temperature extremes.
Recommended
Test and Measurement Instrumentation
Bench-top and rack-mount test equipment - oscilloscopes, logic analyzers, signal generators, and protocol analyzers - often use Altera FPGAs for high-speed DSP and protocol decoding, with the EPC2LI20 providing reliable field-upgradable boot memory. The IEEE 1532 JTAG interface allows in-system reprogramming when new measurement firmware is released, without removing the instrument from service. The on-chip decompression engine compresses large FPGA images so that the 1.6 Mb flash budget still fits dense logic-plus-DSP designs typical of high-end T&M gear.
Recommended
Multi-FPGA Daisy-Chain Configuration
When a board carries multiple Altera FPGAs that must boot in lockstep, the EPC2LI20 controller can cascade configuration data out to a chain of downstream devices using the standard serial/byte-wide configuration protocol. Because the on-chip flash can hold compressed bitstreams for several FPGAs, a single EPC2LI20 often suffices to boot two or three FPGAs, simplifying PCB routing and BOM. This architecture is common in DSP co-processing boards, image-processing pipelines, and high-channel-count telecom gear where multiple FPGAs share a single boot source.
Recommended
User Non-Volatile Memory for Nios II / PLD Systems
Beyond configuration storage, the EPC2LI20 exposes unused flash space to user logic, allowing a Nios II embedded processor or external PLD to use the device as general-purpose non-volatile memory for parameters, lookup tables, calibration data, or bootloader images. According to the Altera datasheet, the controller arbitrates between configuration reads and user read/write access, so a single EPC2LI20 can serve as both the FPGA's boot source and the system's parameter store. This reduces component count on space-constrained boards that would otherwise need a separate EEPROM.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LI20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2LC20 | EPC2LI20N | EPC20LI20N | EPC1LI20 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 20-PLCC (9x9) | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same |
| Memory Size | 1.6 Mb | 1.6 Mb | 1.6 Mb | 1.6 Mb | 1.6 Mb | 1 Mb |
| Operating Temperature | -40 C to +85 C | 0 C to +70 C (commercial N variant) | 0 C to +70 C (commercial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Supply Voltage | 3.0-3.6 V / 4.5-5.5 V | 3.0-3.6 V / 4.5-5.5 V | 3.0-3.6 V / 4.5-5.5 V | 3.0-3.6 V / 4.5-5.5 V | 3.0-3.6 V / 4.5-5.5 V | 3.0-3.6 V / 4.5-5.5 V |
| Programmable Type | In System Programmable (ISP) | In System Programmable (ISP) | In System Programmable (ISP) | In System Programmable (ISP) | In System Programmable (ISP) | In System Programmable (ISP) |
| On-chip Decompression | Yes | Yes | Yes | Yes | Yes | No |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND / Obsolete |
Key Differentiators
- Industrial temperature rating on PLCC-20 footprint (vs EPC2LC20)
- 1.6 Mb density with on-chip decompression (vs EPC1LI20)
- Drop-in compatibility within the EPC2 family (vs EPC2LC20N)
Design Notes
Place a 0.1 uF decoupling capacitor as close as practical to the VCC and VPP pins of the EPC2LI20, with a short ground return directly to the GND pin. The PLCC-20 package allows socketed mounting, which simplifies factory programming and field replacement; use a low-profile PLCC socket (e.g., 3M Textool or equivalent) when the board must be re-flashed frequently. Keep JTAG traces short and route TDI/TDO as a daisy chain through all programmable devices on the board to preserve signal integrity at TCK frequencies up to 10 MHz.
The DATA output of the EPC2LI20 drives the FPGA's DATA0 pin; for byte-wide (parallel) configuration, route the 8 data bits with matched trace lengths (within 50 mil) to minimize skew between bits. DCLK should be treated as a clock signal: route it on an inner layer with a continuous ground reference and avoid crossing splits. Series-terminate DCLK and DATA with 33 ohm resistors near the source if the trace length exceeds 2 inches to dampen ringing on long backplane connections.
Do not confuse the EPC2LI20 (industrial temperature) with the EPC2LC20 (commercial temperature) when sourcing for harsh-environment designs - both share the same PLCC-20 footprint but differ in operating temperature. Confirm the full ordering code (e.g., EPC2LI20 vs EPC2LI20N) matches your BOM, because 'N' suffix typically denotes a lead-free/RoHS variant. Do not assume EPC2 PROMs can be replaced pin-for-pin by EPCQ or EPCQ-A devices without PCB rework - the EPCQ family uses a smaller 8/16-pin SOIC footprint, not PLCC-20.
The EPC2LI20's internal voltage-sense circuitry selects 3.3V vs 5.0V operation automatically, but the VCC and VPP pins must both be tied to the same supply rail (or VPP to a slightly higher programming voltage during ISP). Avoid leaving VPP floating; tie VPP to VCC through a 0 ohm resistor or short trace to prevent spurious ISP-mode entry. During power-up ramp, hold nCONFIG low until VCC reaches the minimum operating threshold to prevent undefined configuration states on the FPGA.
Compliance Information
RoHS/REACH compliance status was not stated in the verified web data; verify with the manufacturer or distributor (DigiKey/Altera) before designing into RoHS-bound products. AEC-Q100 is not applicable because the EPC2LI20 is a memory/configuration device, not an automotive-qualified IC.
