EPC2LC20 vs EPC1L20 Comparison
Detailed side-by-side comparison of EPC2LC20 by Altera and EPC1L20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LC20 | EPC1L20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $3.75 |
| Memory Type | Non-volatile configuration PROM | OTP Configuration PROM (Flash) |
| Memory Size | 1.6 Mbit | 1 Mbit |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | β |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | β |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | β |
| ISP Voltage Range | 5.0 V or 3.3 V | β |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | β |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | β |
| Package | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin PLCC (9x9 mm) |
| Mounting Type | Surface Mount | Through-Hole / Socket |
| Operating Temperature | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | β |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | β |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | β |
| Configuration Clock (max) | β | 8 MHz |
| Flash Access Time | β | 90 ns (approx.) |
| Max Read Bandwidth | β | 160 Mbps (16-bit DQ bus) |
| Interface | β | Serial / FPP configuration + JTAG (IEEE 1149.1) |
| Supply Voltage | β | 3.3 V (typical) |
| Programmability | β | One-Time Programmable (OTP) |
| JTAG / ISP Support | β | Yes (IEEE 1149.1) |
| Compatible FPGA Series | β | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |