EPC2LC20 vs EPC1LC120 Comparison
Detailed side-by-side comparison of EPC2LC20 by Altera and EPC1LC120 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC1LC120
EPC1LC120 - 1Mb SRAM Config Memory, 8MHz, 120-Pin LQFP | Altera
EPC1LC120 β ActiveSpecification Comparison
| Parameter | EPC2LC20 | EPC1LC120 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $9.30 |
| Memory Type | Non-volatile configuration PROM | Serial Configuration Memory (Flash-based, non-volatile) |
| Memory Size | 1.6 Mbit | β |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | β |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | β |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | β |
| ISP Voltage Range | 5.0 V or 3.3 V | β |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | β |
| Package | 20-pin PLCC (J-lead, 9x9 mm) | LQFP-120 (Low-profile Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | β |
| RoHS Status | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | β |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | β |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | β |
| Memory Density | β | 1 Mbit |
| Serial Clock Frequency (DCLK) | β | 8 MHz |
| Interface | β | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | β | [DATA_NEEDED: VCC range] |
| Programming | β | Factory / JTAG via Altera programming tools |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Configuration Mode | β | Serial configuration of SRAM-based FPGAs |
| Compatible Bitstream Width | β | Serial |