EPC2LC20CAD vs EPC2LC20 Comparison
Detailed side-by-side comparison of EPC2LC20CAD by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LC20CAD | EPC2LC20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $7.20 |
| Memory Type | Configuration PROM (Flash) | Non-volatile configuration PROM |
| Memory Capacity | 1.6 Mbit | β |
| Supply Voltage | 3.3 V (nominal) | β |
| I/O Voltage Tolerance | 5 V tolerant | β |
| Configuration Mode | Serial (bit-wide, Altera FPGAs) | β |
| Program Interface | IEEE Std 1149.1 JTAG (in-system programmable) | β |
| Package | 20-pin J-lead PLCC (PLCC-20) | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Count | 20 | β |
| Operating Temperature | -40C to +85C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Maximum Input Voltage (DC) | -0.3 V to +7.0 V | β |
| Input Undershoot/Overshoot | -2.0 V to +7.0 V for <100 mA, <20 ns no-load | β |
| Compatible FPGA Families | APEX 20K, ACEX 1K, Cyclone, Stratix | β |
| Programming Method | JTAG ISP (no external programmer required) | β |
| RoHS Status | Compliant | Non-Compliant (original Altera Pb-containing part) |
| Mounting Type | Surface Mount / Through-hole (PLCC socket) | Surface Mount |
| Memory Size | β | 1.6 Mbit |
| Configuration Interface | β | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | β | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | β | 5.0 V or 3.3 V |
| Supported FPGA Families | β | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | β | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | β | EPC2LC20N available as lead-free equivalent |
| Programming Support | β | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | β | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |