EPC2LC20ES vs EPC2LC20 Comparison
Detailed side-by-side comparison of EPC2LC20ES by Intel and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2LC20ES
EPC2LC20ES - 1.6Mb ISP Config PROM for FPGAs | Intel / Altera
EPC2LC20ES β Active
Specification Comparison
| Parameter | EPC2LC20ES | EPC2LC20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.85 | $7.20 |
| Memory Type | Configuration PROM (Non-volatile) | Non-volatile configuration PROM |
| Memory Size | 1.6 Mbit | 1.6 Mbit |
| Target Device | SRAM-based FPGAs and LUT devices | β |
| Interface | Serial (DCLK/DATA) with JTAG ISP | β |
| Operating Voltage | 3.3 V and 5.0 V tolerant | β |
| JTAG Standard | IEEE Std. 1149.1 compliant | β |
| In-System Programmability | Yes (via built-in JTAG) | β |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | β |
| Configuration Modes | Serial and parallel supported | β |
| Package | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| Pin Count | 20 | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| RoHS Status | Compliant (ES suffix denotes lead-free industrial) | Non-Compliant (original Altera Pb-containing part) |
| Programming Interface | JTAG (4-wire: TDI/TDO/TMS/TCK) | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Manufacturer | Intel (formerly Altera) | β |
| Configuration Interface | β | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | β | 5.0 V or 3.3 V |
| Supported FPGA Families | β | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | β | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | β | EPC2LC20N available as lead-free equivalent |
| Programming Support | β | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | β | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |