EPC2LC20ES - 1.6Mb ISP Config PROM for FPGAs | Intel / Altera
MPN: EPC2LC20ES ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $8.05 | $80.50 |
| 100 | $7.1 | $710.00 |
| 500 | $6.4 | $3,200.00 |
| 1,000 | $5.85 | $5,850.00 |
EPC2LC20ES Overview
A Configuration PROM (Programmable Read-Only Memory) for FPGAs is a non-volatile serial memory device that holds the FPGA's configuration bitstream. When the FPGA powers up, it reads its configuration data from the PROM via a serial or parallel configuration interface. These devices sit in the broader memory hierarchy as: PROM -> non-volatile memory -> configuration memory -> FPGA support IC, and are essential for standalone FPGA designs that need to self-configure without an external microprocessor or download cable.
Key features of the EPC2LC20ES include 1.6 Mbit storage capacity suitable for mid-density Altera FPGAs such as the ACEX 1K, APEX 20K, Cyclone, and Mercury families, JTAG-based ISP that allows field upgrades without removing the device, and built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1. The device supports both DCLK-based serial and parallel configuration modes, providing flexibility across multiple FPGA targets. Low standby current and 3.3 V/5 V tolerance make it well suited for mixed-voltage system designs.
Architecturally, the EPC2LC20ES uses a serial interface with a built-in oscillator and state machine that streams configuration data to the FPGA through the DATA, DCLK, and nCONFIG/nSTATUS control signals. The on-chip JTAG TAP controller enables both ISP and boundary-scan test access. The PROM operates as a slave device on the JTAG chain, allowing multiple devices to be programmed and verified in a single boundary-scan pass.
Typical applications include configuration storage for Altera ACEX 1K, APEX 20K, Cyclone, Mercury, and Stratix-class FPGAs, factory-floor JTAG programming stations, and field-upgradable embedded systems. Designers also use this PROM in industrial controllers and military/aerospace prototypes where a self-booting FPGA is required without an external configuration controller.
When designing with this device, note that the EPC2LC20ES is rated for industrial temperature range and ships as a lead-free PLCC-20 J-leaded package for through-hole or socketed mounting. The device is in production but considered a legacy Altera configuration solution; for new designs, designers should evaluate Altera/Intel EPCQ-series serial configuration devices (AS mode) for newer FPGA families.
This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers quickly validate EPC2LC20ES as a configuration memory solution for legacy and current Altera FPGA designs.
Drop-in alternatives for EPC2LC20ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20ES (same form factor and footprint) — differing in Package, Memory Type, Mounting Type, Interface, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20EM
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1441LC20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC16QI100
✅ Drop-In✓ In Stock
$15.4 / Unit
View Datasheet →XC17S20PD8I
✅ Drop-In📋 Reference alternative (not in catalog)
EPC2LC20ES Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration PROM (Non-volatile) |
| Memory Size | 1.6 Mbit |
| Target Device | SRAM-based FPGAs and LUT devices |
| Interface | Serial (DCLK/DATA) with JTAG ISP |
| Operating Voltage | 3.3 V and 5.0 V tolerant |
| JTAG Standard | IEEE Std. 1149.1 compliant |
| In-System Programmability | Yes (via built-in JTAG) |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant |
| Configuration Modes | Serial and parallel supported |
| Package | 20-PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount / Through-Hole (PLCC socket) |
| Pin Count | 20 |
| RoHS Status | Compliant (ES suffix denotes lead-free industrial) |
| Programming Interface | JTAG (4-wire: TDI/TDO/TMS/TCK) |
| Manufacturer | Intel (formerly Altera) |
EPC2LC20ES Pin Configuration
| Pin 1 | DATA — Serial data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nCONFIG — Configuration control (active low) |
| Pin 4 | nSTATUS — Configuration status (active low) |
| Pin 5 | CONF_DONE — Configuration done indicator |
| Pin 6 | TDI — JTAG test data input |
| Pin 7 | TDO — JTAG test data output |
| Pin 8 | TMS — JTAG test mode select |
| Pin 9 | TCK — JTAG test clock |
| Pin 10 | GND — Ground |
| Pin 11 | VCC — Supply voltage (3.3 V) |
| Pin 12 | OE — Output enable (active low) |
| Pin 13 | nCS — Chip select (active low) |
| Pin 14 | A0 — Address line 0 (parallel mode) |
| Pin 15 | A1 — Address line 1 (parallel mode) |
| Pin 16 | A2 — Address line 2 (parallel mode) |
| Pin 17 | A3 — Address line 3 (parallel mode) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | NC — Not connected (per datasheet) |
Typical Applications
EPC2LC20ES is suitable for 6 applications: Altera ACEX 1K FPGA Configuration, Altera Cyclone FPGA Standalone Boot, APEX 20K Multi-Device JTAG Programming, Mercury-Class FPGA Config Storage, JTAG Boundary-Scan Test (BST) Station, Legacy Industrial Controller Self-Boot.
Altera ACEX 1K FPGA Configuration
The EPC2LC20ES's 1.6 Mbit density and DCLK-serial interface match the ACEX 1K family's compressed bitstream size and configuration mode, enabling standalone boot. According to the Altera configuration datasheet, the PROM connects to the FPGA's MSEL/DATA/DCLK/nCONFIG pins in PS (passive serial) mode, streaming bitstream at the FPGA's internal oscillator rate (typ. 20 MHz). The PROM's 3.3 V/5 V tolerance supports both ACEX 1K core voltages, and the JTAG ISP allows field upgrades without removing the PROM from the socketed PLCC.
Recommended
Altera Cyclone FPGA Standalone Boot
The EPC2LC20ES can configure small to mid-density Cyclone FPGAs (EP1C3, EP1C6) in passive serial mode by streaming the compressed .sof bitstream through the DATA/DCLK pins. The PROM's 1.6 Mbit storage holds typical Cyclone bitstreams after compression, and its industrial temperature grade suits factory automation environments. According to Altera configuration guidelines, MSEL pins must be set to PS configuration mode; nCONFIG toggles reset, and CONF_DONE from the FPGA signals successful completion back through the JTAG chain for verification.
Recommended
APEX 20K Multi-Device JTAG Programming
The EPC2LC20ES's built-in IEEE 1149.1 JTAG TAP allows it to be chained with APEX 20K FPGAs and other boundary-scan devices for in-system programming of multi-FPGAs boards. According to the Altera configuration datasheet, the JTAG chain order is programmable, allowing the PROM to be re-flashed via USB-Blaster without removing the board from the chassis. This is essential for APEX 20K designs in telecom and military systems where field upgrades are required.
Recommended
Mercury-Class FPGA Config Storage
The EPC2LC20ES supports Mercury (EP1M-class) FPGAs through its parallel configuration mode, where the PROM streams 8-bit-wide data on each DCLK cycle for faster configuration of the larger Mercury devices. According to Altera configuration datasheet notes, parallel mode reduces configuration time by ~8x compared to serial, critical for time-to-ready industrial and defense systems. The PROM's PLCC socket allows quick swap-out during development.
Recommended
JTAG Boundary-Scan Test (BST) Station
Built-in IEEE 1149.1 boundary-scan test (BST) circuitry in the EPC2LC20ES allows the PROM to participate in board-level BST for interconnect testing. According to the Altera configuration devices datasheet, the PROM's BSDL file describes its boundary-scan cells on TDI/TDO, allowing JTAG testers to verify shorts, opens, and stuck-at faults on configuration signal traces. This is critical for high-reliability boards in aerospace, medical, and automotive applications where boundary-scan coverage is mandated.
Recommended
Legacy Industrial Controller Self-Boot
The EPC2LC20ES enables FPGA-based industrial controllers (PLC, motion controllers, SCADA front-ends) to self-boot without an external microprocessor or download cable. According to the Altera configuration datasheet, the PROM's industrial temperature grade and 20-PLCC socketed package simplify field replacement. At power-up the FPGA reads its bitstream from the PROM in passive serial mode, eliminating the need for a configuration controller and reducing BOM cost in long-life industrial systems where 10+ year field support is required.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20 | EPC2LC20EM | EPC1LC20 | EPC1441LC20 | XC17S20PD8I |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | AMD / Xilinx |
| Package | 20-PLCC (9x9 mm) | 20-PLCC (same) | 20-PLCC (same) | 20-PLCC (same) | 20-PLCC (same) | 8-DIP (different) |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | ~1 Mbit | ~0.4 Mbit | 1.3 Mbit |
| Interface | Serial + JTAG ISP | Serial + JTAG ISP | Serial + JTAG ISP | Serial + JTAG ISP | Serial + JTAG ISP | Serial (Xilinx) |
| Operating Voltage | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V |
| JTAG ISP (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes | No (Xilinx Slave Serial) |
| RoHS Compliance | Yes (lead-free ES) | Depends on variant | Yes | Depends on variant | Depends on variant | Yes |
| Target FPGA Family | Altera ACEX/APEX/Cyclone/Mercury | Altera ACEX/APEX/Cyclone/Mercury | Altera ACEX/APEX/Cyclone/Mercury | Altera FLEX 10K-class | Altera FLEX 6000-class | Xilinx Spartan/Virtex |
Key Differentiators
- Lead-free ES variant for RoHS markets (vs EPC2LC20 (standard SnPb))
- 1.6 Mbit density fits mid-density Altera FPGAs (vs EPC1LC20 (~1 Mbit))
- IEEE 1149.1 JTAG with BST support (vs XC17S20PD8I (Xilinx))
Design Notes
Mount the EPC2LC20ES in a 20-pin PLCC socket (e.g. 3M Textool or Aries) to allow quick field replacement and in-system reprogramming. Keep the DATA and DCLK traces to the FPGA short (less than 50 mm) and route them as a matched-length pair to avoid signal skew. Place a 0.1 uF decoupling capacitor adjacent to the VCC pin and a 10 uF bulk capacitor on the same supply rail. Tie nCONFIG through a 1 kohm pull-up to VCC and CONF_DONE through a 10 kohm pull-up to allow the FPGA to override these signals during programming.
Do not confuse the EPC2LC20ES with the EPC2LC20A or EPC2LI20 variants - the A-suffix denotes different density and the LI20 denotes an older FLEX 10KA-compatible PROM. Always verify the compressed bitstream size fits within the PROM's 1.6 Mbit capacity; for larger designs use EPC4 or EPC8/EPC16 PROMs with the same 20-PLCC footprint family. According to the Altera configuration datasheet, MSEL pins on the FPGA must match the PROM's serial/parallel mode; a mismatch causes configuration failure.
JTAG chain integrity is critical for in-system programming. According to the Altera configuration devices datasheet, keep the JTAG TDI-TDO daisy chain under 6 inches per segment to avoid signal integrity issues, and place a 10 kohm pull-up on TMS and TCK lines. For boards with long JTAG chains, use a JTAG buffer such as the SN74LVC1G125 to isolate segments. Always include a JTAG header (10-pin or 14-pin Altera-compatible) accessible from the board edge for programming access.
Compliance Information
ES suffix denotes lead-free finish per Altera/Intel ordering info. RoHS compliance per Alldatasheet listing. AEC-Q100 not applicable (configuration memory is not a safety-critical automotive part).
