EPC2LI20PULLS vs EPC2LI20N Comparison
Detailed side-by-side comparison of EPC2LI20PULLS by Intel and EPC2LI20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2LI20PULLS
EPC2LI20PULLS - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel
EPC2LI20PULLS ObsoleteSpecification Comparison
| Parameter | EPC2LI20PULLS | EPC2LI20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $5.10 |
| Memory Type | Serial Configuration Flash PROM | Non-volatile configuration PROM (Flash) |
| Memory Size | 1.6 Mbit | 1.6 Mbit |
| Configuration Interface | Serial (Altera FPP / PS modes) | β |
| Maximum Clock Frequency | 10 MHz | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | β |
| I/O Tolerance | 5 V tolerant configuration pins | β |
| Programmability | In-system via IEEE 1149.1 JTAG | β |
| Compression Support | Yes (real-time decompression in target FPGA) | β |
| Multi-Device Cascade | Yes (daisy-chain supported) | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Package | 20-pin PLCC (J-Lead, 9x9 mm) | β |
| Mounting Type | Surface Mount / Socket | Surface Mount |
| MSL Level | 3 (168 hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | β |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur | β |
| Programmable Type | β | In System Programmable (ISP via JTAG) |
| Configuration Mode | β | Serial |
| Maximum Configuration Frequency | β | 10 MHz |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | β | 4.5 V to 5.5 V |
| Package / Case | β | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | β | Tube |
| Supported FPGA Series | β | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | β | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | β | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |