EPC2LI20U vs EPC1441LI20 Comparison
Detailed side-by-side comparison of EPC2LI20U by Altera and EPC1441LI20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LI20U | EPC1441LI20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $8.10 |
| Memory Type | Configuration PROM (serial EEPROM) | OTP Configuration PROM (PROM) |
| Memory Size | 1.6 Mbit (65,536 x 1-bit device) | β |
| Supply Voltage (VCC) | 3.0 V to 5.5 V (5.0 V nominal) | β |
| Programming Voltage | 5.0 V (via internal charge pump) | β |
| Configuration Interface | Serial 4-pin (DATA, DCLK, nCS, OE) | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Maximum DCLK Frequency | 33 MHz (fast mode) | β |
| Operating Temperature Range | -40 C to +85 C (industrial) | β |
| Package | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount (PLCC socket) | β |
| Programmability | In-system programmable via JTAG (IEEE 1149.1) | β |
| Cascade Support | Yes (via nCASC pin) | β |
| Device ID | 32-bit JTAG-readable | β |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Density | β | 441 kbits (440,800 bits) |
| Number of Words | β | 440,800 |
| Bits per Word | β | 1 bit |
| Supply Voltage | β | 3.3 V |
| Operating Temperature | β | -40 C to +85 C (industrial) |
| Pin Pitch | β | 1.27 mm |
| Programming Method | β | One-Time-Programmable via Altera programming hardware |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Configuration Time | β | Depends on FPGA bitstream length and DCLK frequency |