EPC2LI20U - 1.6Mb In-System Prog Config PROM | Altera | FPGA
MPN: EPC2LI20U ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
EPC2LI20U Overview
A configuration PROM is a non-volatile serial memory device that stores the FPGA's bitstream and loads it into the SRAM-based logic fabric at power-up. Because Altera SRAM-based LUT devices (APEX II, APEX 20K family, Mercury, ACEX 1K, and FLEX 6000/10KE/10KA) lose configuration when power is removed, an external configuration memory such as the EPC2LI20U is required to reload the device on every power-up cycle. The EPC2 family uses a simple 4-pin serial interface (DATA, DCLK, nCS, and OE) for easy connection to the FPGA's configuration pins.
Key features include 1.6Mb storage density (sufficient for mid-density FPGAs), in-system programmability via IEEE 1149.1 JTAG, cascading capability to support larger bitstreams via dedicated nCASC pin, and 5.0V tolerant I/O on a 3.3V core supply. The device supports a serial configuration clock (DCLK) up to 33 MHz in fast mode and 17 MHz in standard mode, enabling rapid FPGA initialization. The PLCC-20 package provides through-hole compatibility for legacy designs and industrial systems.
The EPC2 architecture uses a serial EEPROM-based storage array with on-chip charge pump for programming voltage generation. The in-system programmability eliminates the need for separate PROM programmers, reducing manufacturing cost and enabling field firmware updates through the JTAG chain. Each device is identified by a unique 32-bit device ID readable through JTAG for board-level traceability.
Typical applications include configuring Altera APEX 20K, ACEX 1K, Mercury, and FLEX 6000/10KE/10KA FPGAs in telecommunications equipment, industrial control systems, test and measurement instrumentation, and legacy military/aerospace systems. The wide 3.3V-5.0V supply range allows the PROM to share the FPGA's programming voltage rail, simplifying board design.
When designing with the EPC2LI20U, ensure that the nCS, DCLK, DATA, and OE traces are routed as short as possible to minimize skew and maintain signal integrity at the maximum DCLK frequency. For bitstreams exceeding 1.6Mb, cascade a second EPC2 device using the nCASC pin. Verify JTAG chain ordering to avoid configuration failures when multiple devices share the same programming bus.
This page synthesizes distributor stock data, same-brand drop-in alternatives, and practical board-level design notes not aggregated in the Altera configuration handbook.
Drop-in alternatives for EPC2LI20U — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LI20U (same form factor and footprint) — differing in Memory Type, Memory Size, Mounting Type, Package, Configuration Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LI20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$5.95 / Unit
View Datasheet →EPC2LI20N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LI20J
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.75 / Unit
View Datasheet →EPC2L20U
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.55 / Unit
View Datasheet →EPC2LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.2 / Unit
View Datasheet →EPC1441LI20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$8.1 / Unit
View Datasheet →EPC2LI20U Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration PROM (serial EEPROM) |
| Memory Size | 1.6 Mbit (65,536 x 1-bit device) |
| Supply Voltage (VCC) | 3.0 V to 5.5 V (5.0 V nominal) |
| Programming Voltage | 5.0 V (via internal charge pump) |
| Configuration Interface | Serial 4-pin (DATA, DCLK, nCS, OE) |
| Maximum DCLK Frequency | 33 MHz (fast mode) |
| Operating Temperature Range | -40 C to +85 C (industrial) |
| Package | 20-pin PLCC (9x9 mm) |
| Mounting Type | Surface Mount (PLCC socket) |
| Programmability | In-system programmable via JTAG (IEEE 1149.1) |
| Cascade Support | Yes (via nCASC pin) |
| Device ID | 32-bit JTAG-readable |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
EPC2LI20U Pin Configuration
| Pin 1 | DATA — Serial data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | VCC — Power supply (3.0V to 5.5V) |
| Pin 4 | nCS — Chip select (active low) |
| Pin 5 | GND — Ground |
| Pin 6 | OE — Output enable (active low) |
| Pin 7 | nCASC — Cascade output (active low) |
| Pin 8 | nINIT_CONF — Initiate configuration (active low) |
| Pin 9 | nCE — Chip enable (active low) |
| Pin 10 | TDI — JTAG test data input |
| Pin 11 | TMS — JTAG test mode select |
| Pin 12 | TCK — JTAG test clock |
| Pin 13 | TDO — JTAG test data output |
| Pin 14 | NC — Not connected |
| Pin 15 | NC — Not connected |
| Pin 16 | NC — Not connected |
| Pin 17 | NC — Not connected |
| Pin 18 | VPP — Programming voltage (internal charge pump) |
| Pin 19 | GND — Ground |
| Pin 20 | VCC — Power supply (3.0V to 5.5V) |
Typical Applications
EPC2LI20U is suitable for 7 applications: APEX 20K FPGA Configuration, FLEX 10KE / 10KA FPGA Boot Memory, ACEX 1K FPGA Configuration, Mercury FPGA Configuration (Legacy), APEX II FPGA Configuration, Industrial Control Systems, Test & Measurement Equipment.
APEX 20K FPGA Configuration
The EPC2LI20U stores the configuration bitstream for Altera APEX 20K, APEX 20KC, and APEX 20KE FPGAs, providing 1.6Mb of non-volatile serial memory. The 33 MHz DCLK capability enables rapid configuration times under 100ms for typical APEX 20K bitstreams. The 4-pin serial interface (DATA, DCLK, nCS, OE) directly drives the FPGA's PS (Passive Serial) configuration pins without external glue logic. Industrial temperature rating supports factory automation, telecommunications, and outdoor equipment deployments.
Recommended
FLEX 10KE / 10KA FPGA Boot Memory
The EPC2LI20U configures Altera FLEX 10KE and FLEX 10KA FPGAs at power-up, supplying the 1.6Mb bitstream required for medium-density designs in the EPF10K50 to EPF10K100 range. The 3.0V-5.5V supply range matches the FLEX 10K family's 5.0V tolerant configuration interface, eliminating level shifters. The PLCC-20 package supports through-hole socket mounting for field-serviceable industrial designs. JTAG-based in-system programming enables firmware updates without removing the board from service.
Recommended
ACEX 1K FPGA Configuration
The EPC2LI20U provides the configuration memory for Altera ACEX 1K EP1K10, EP1K30, and EP1K50 FPGAs, with 1.6Mb capacity exceeding most ACEX 1K compressed bitstreams. The serial 4-pin interface connects directly to the ACEX 1K MSEL[2:0] configuration mode pins set for Passive Serial mode. Wide 3.0V-5.5V supply supports both 3.3V and 5.0V ACEX 1K designs. Cascade capability via nCASC enables configuration of larger bitstreams for ACEX 1K100 devices by chaining two PROMs in series.
Recommended
Mercury FPGA Configuration (Legacy)
The EPC2LI20U supports Altera Mercury EP1M120 FPGAs, the radiation-tolerant variant of the APEX 20KE architecture. The 1.6Mb density accommodates Mercury bitstreams with ECC and scrubbing overhead. Industrial -40C to +85C temperature rating meets aerospace ground-support equipment and military system requirements. In-system programmability via JTAG supports field firmware updates critical for deployed military systems where PROM removal is operationally impractical.
Recommended
APEX II FPGA Configuration
The EPC2LI20U configures Altera APEX II EP2A15, EP2A25, and EP2A40 FPGAs when cascaded with a second EPC2 device via the nCASC pin, providing the combined 3.2Mb+ density required for these high-logic-density devices. The 33 MHz DCLK fast mode minimizes configuration time, critical for time-sensitive boot applications. Industrial temperature grade supports deployment in unconditioned outdoor enclosures. JTAG chain inclusion enables single-point programming of both the FPGA and PROM from the same JTAG header.
Recommended
Industrial Control Systems
The EPC2LI20U boots Altera FPGAs in PLC, motor drive, and SCADA systems where reliable power-up configuration is required. The industrial -40C to +85C temperature range supports factory floor environments with wide thermal swings. PLCC-20 socket mounting allows field replacement of failed PROMs without desoldering, minimizing production line downtime. The 5.0V tolerance accommodates legacy 5V FPGA designs common in long-lifecycle industrial platforms. In-system programming via JTAG supports remote firmware updates over industrial Ethernet.
Recommended
Test & Measurement Equipment
The EPC2LI20U configures Altera FPGAs in oscilloscopes, logic analyzers, and signal generators, where deterministic power-up behavior is critical. The 1.6Mb capacity supports mid-density bitstreams for instrument DSP and data acquisition pipelines. The PLCC-20 package allows socketed programming during manufacturing test, enabling per-unit firmware customization. Wide voltage tolerance supports mixed 3.3V/5.0V analog and digital sections. JTAG programming supports factory calibration bitstream loading.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LI20U — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LI20 | EPC2LI20N | EPC2LI20J | EPC2L20U | EPC2LC20 | EPC1441LI20 |
|---|---|---|---|---|---|---|---|
| Package | 20-pin PLCC (9x9) | 20-pin PLCC (9x9) - same | 20-pin PLCC (9x9) - same | 20-pin PLCC (9x9) - same | 20-pin PLCC (9x9) - same | 20-pin PLCC (9x9) - same | 20-pin PLCC - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 440 Kbit (-72%) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Supply Voltage | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V | 3.3V only | 3.0V to 5.5V |
| In-System Programmable (JTAG) | Yes | Yes | Yes | Yes | No (no 'I' suffix) | Yes | Yes |
| Maximum DCLK Frequency | 33 MHz | 33 MHz | 33 MHz | 33 MHz | 33 MHz | 33 MHz | 33 MHz |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade (-40C to +85C) versus commercial EPC2LI20 (vs EPC2LI20)
- In-system programmable via JTAG (IEEE 1149.1) (vs EPC2L20U)
- Wide 3.0V to 5.5V supply versus 3.3V-only EPC2LC20 (vs EPC2LC20)
Design Notes
Route the 4-pin configuration interface (DATA, DCLK, nCS, OE) as short and direct as possible, ideally under 50mm trace length, to maintain signal integrity at the maximum 33 MHz DCLK frequency. Keep these traces away from switching power supply nodes and high-speed digital signals to avoid coupling that could corrupt the configuration bitstream. Use a ground guard trace between DATA and DCLK if routing density forces close proximity.
When cascading two EPC2LI20U devices for bitstreams exceeding 1.6Mb, connect the nCASC pin of the master PROM to the nCS pin of the slave PROM. Verify that the FPGA's configuration controller releases nSTATUS and drives nCONFIG properly during power-up; a stuck nCONFIG low will prevent configuration. Include a pull-up on nINIT_CONF if not driven by the FPGA during JTAG programming.
The EPC2LI20U dissipates approximately 50mW during active configuration and less than 1mW in standby. The 20-pin PLCC package has a thermal resistance of approximately 50 C/W, well within the industrial -40C to +85C operating range without heatsinking. For enclosed industrial designs with ambient temperatures approaching 85C, ensure adequate ventilation or derate by 10C to account for self-heating in close-packed boards.
Compliance Information
RoHS and REACH compliance not explicitly confirmed in verified data. The 'N' and 'J' suffix variants (EPC2LI20N, EPC2LI20J) indicate lead-free finishes, suggesting the EPC2LI20U base part may not be lead-free. AEC-Q100 not applicable - this is a configuration PROM, not an automotive-grade component.
