EPM3128ATC100-10N vs EPM3128ATC100-10NS Comparison
Detailed side-by-side comparison of EPM3128ATC100-10N by Altera and EPM3128ATC100-10NS by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndSpecification Comparison
| Parameter | EPM3128ATC100-10N | EPM3128ATC100-10NS |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.20 | $6.50 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macro Cells | 128 | 128 |
| Usable Gates | 2500 | β |
| Number of I/O | 80 | β |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency (fMAX) | 98 MHz | β |
| Supply Voltage VCCINT | 3.3 V | β |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | β |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | EEPROM (non-volatile) |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | β |
| Package | 100-pin TQFP (14 x 14 x 1.0 mm) | TQFP-100 |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| MSL Level | 3 (per JEDEC J-STD-020) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| User I/Os | β | 80 |
| Pin Count | β | 100 |
| Pin-to-Pin Logic Delay (tPD) | β | 10 ns |
| Counter Frequency (fCNT) | β | up to 227.3 MHz |
| Supply Voltage - Core (VCCINT) | β | 3.3 V |
| Supply Voltage - I/O (VCCIO) | β | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic-Level Compatibility | β | 5.0 V, 3.3 V, 2.5 V |
| Programmability | β | In-system (ISP), IEEE Std. 1532 |
| Boundary Scan | β | IEEE 1149.1 JTAG |