EPM3128ATC100-7N vs EPM3128ATC100-10N Comparison

Detailed side-by-side comparison of EPM3128ATC100-7N by Intel and EPM3128ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC100-7N EPM3128ATC100-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $3.52 $5.20
Family MAX 3000A MAX 3000A
Macro Cells 128 128
Usable Gates Up to 10,000 2500
Number of I/Os 80 β€”
Number of Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] β€”
Propagation Delay (tPD) 7.5 ns 10 ns
Counter Frequency (max) 227.3 MHz β€”
Supply Voltage - Core 3.3 V β€”
I/O Interface Levels 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) β€”
In-System Programmability Yes (IEEE 1532 / JTAG) β€”
Program Memory Type EEPROM (non-volatile) β€”
Operating Temperature 0C to +70C (Commercial) 0 Β°C to +70 Β°C (commercial)
Package TQFP-100 (100-pin TQFP, fine-line BGA-256 noted in third-party listings) 100-pin TQFP (14 x 14 x 1.0 mm)
Mounting Type Surface Mount Surface Mount
Logic Family CMOS β€”
Speed Grade -7 β€”
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Product Type β€” CPLD (Complex Programmable Logic Device)
Number of I/O β€” 80
Logic Elements / Blocks β€” 8 LABs (16 macrocells each)
Maximum Internal Frequency (fMAX) β€” 98 MHz
Supply Voltage VCCINT β€” 3.3 V
I/O Bank Voltage VCCIO β€” 3.3 V or 2.5 V (selectable)
Configuration Memory β€” CMOS EEPROM (non-volatile, instant-on)
In-System Programming β€” IEEE Std. 1532-compliant ISP via JTAG
Lead-Free β€” Yes
MSL Level β€” 3 (per JEDEC J-STD-020)

Datasheets & Resources

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