EPM5192AQC-1 vs EPM5192AQI100-20 Comparison
Detailed side-by-side comparison of EPM5192AQC-1 by Altera and EPM5192AQI100-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AQC-1 | EPM5192AQI100-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.40 | $18.90 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | One-Time Programmable (OTP) CPLD | β |
| Macrocells | 192 | β |
| Logic Elements / Logic Array Blocks | [DATA_NEEDED: number of LABs] | β |
| Propagation Delay (tPD) | 40 ns | β |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX value] | β |
| User I/O Pins | 64 | β |
| Dedicated Inputs | 7 | 7 |
| Total Inputs / Outputs | 72 inputs / 64 outputs | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Nominal Supply Voltage | 5 V | β |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) | β |
| Package | PQFP-100 (Plastic Quad Flat Pack) | 100-pin PQFP (R-PQFP-G100) |
| Terminal Pitch | 0.635 mm | β |
| Technology | CMOS, UV-Erasable / OTP EPROM | CMOS, UV-erasable EPROM |
| Configuration Method | One-Time Programmable (OTP) / UV-Erasable | β |
| Mounting Type | Surface Mount | Surface Mount (PQFP) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Device Series | β | EPM5192 |
| Propagation Delay | β | 20 ns (speed grade -20) |
| Logic Array Blocks (LABs) | β | 12 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Macrocell Count | β | 192 |
| I/O Pins | β | 64 bidirectional |
| JEDEC Package Outline | β | R-PQFP-G100 |
| Operating Temperature | β | Industrial grade ("I" suffix) |
| Architecture | β | Classic EPLD, deterministic timing |
| Design Tool | β | Altera MAX+PLUS II (legacy) |
| Supply Voltage | β | [DATA_NEEDED: VCC range] |