EPM5192AQC-1 - 192-Macrocell CMOS OTP PLD | Altera MAX 5000
MPN: EPM5192AQC-1 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $19.1 | $9,550.00 |
| 1,000 | $17.4 | $17,400.00 |
EPM5192AQC-1 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines multiple PLA-style macrocell blocks on a single die with a central interconnect. Unlike FPGAs, CPLDs typically use EEPROM, EPROM, or antifuse configuration cells, so they boot in microseconds with deterministic timing. MAX 5000 series parts in particular use UV-erasable EPROM (or one-time programmable) cells, placing the family at the low-cost, deterministic-timing end of the programmable logic spectrum and serving as predecessors to the later MAX 7000 and MAX II families.
Key specifications include 192 macrocells, 64 bidirectional I/O pins, 40 ns pin-to-pin propagation delay (tPD), and a 5 V Β±5 % supply tolerance. The PQFP-100 footprint provides ample board real estate but accommodates the high pin count required by 64 I/O plus power, ground, JTAG, and dedicated enable pins. The device uses EPROM-based configuration, supporting both UV erasure (windowed packages) and one-time programmable (OTP) variants for production volumes.
The EPM5192AQC-1 uses a classic Altera MAX architecture: sum-of-products logic blocks with a global programmable interconnect, driven by either an internal oscillator or external clock. Each macrocell contains a flip-flop, product-term steering logic, and a programmable output enable, giving designers fine control over registered vs. combinatorial behavior, polarity, and output slew. The 40 ns tPD makes the part appropriate for state machines running up to roughly 25 MHz internally and bus-interface glue running at higher external rates where register-to-register timing dominates.
Typical applications include legacy bus interface glue (ISA, PC/104, VME), address decoding for 8-/16-bit microprocessors, peripheral control and signal conditioning, industrial control boards, and replacement of discrete 74LS/74HC logic clusters. Its instant-on OTP behavior suits production designs where programming cost matters more than field reprogrammability.
Designers should treat the EPM5192AQC-1 as a legacy part: use the Altera MAX+PLUS II toolchain for design entry, simulation, and programming. Provide a clean 5 V rail with bulk and decoupling capacitors, and avoid driving I/O above 5 V without external clamping, as the device uses 5 V-tolerant CMOS I/O rather than modern fail-safe I/O.
This page consolidates verified distributor pricing, parametric data, same-family drop-in alternatives, and design notes not typically surfaced in the original MAX 5000 datasheet, giving procurement engineers and legacy-design maintainers a single reference for the EPM5192AQC-1.
Drop-in alternatives for EPM5192AQC-1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM5192AQC-1 (same form factor and footprint) β differing in Package, Device Type, Propagation Delay (tPD), Mounting Type, Configuration Memory.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192AQC
β Drop-Inπ Reference alternative (not in catalog)
EPM5192AGC-15
β Drop-Inβ In Stock
$27.8 / Unit
View Datasheet βEPM5192AGC-20
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM5192AGC
β Drop-Inβ In Stock
$56 / Unit
View Datasheet βEPM5192AJC-15
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM5192AJC-25
β Drop-Inβ In Stock
$8.2 / Unit
View Datasheet βEPM5192AQC-1 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | One-Time Programmable (OTP) CPLD |
| Macrocells | 192 |
| Propagation Delay (tPD) | 40 ns |
| User I/O Pins | 64 |
| Dedicated Inputs | 7 |
| Total Inputs / Outputs | 72 inputs / 64 outputs |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) |
| Package | PQFP-100 (Plastic Quad Flat Pack) |
| Terminal Pitch | 0.635 mm |
| Technology | CMOS, UV-Erasable / OTP EPROM |
| Configuration Method | One-Time Programmable (OTP) / UV-Erasable |
| Mounting Type | Surface Mount |
EPM5192AQC-1 Pin Configuration
| Pin 1 | I/O β Bidirectional user I/O (macrocell 1) |
| Pin 2 | I/O β Bidirectional user I/O (macrocell 2) |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β Bidirectional user I/O (macrocell 3) |
| Pin 5 | I/O β Bidirectional user I/O (macrocell 4) |
| Pin 6 | I/O β Bidirectional user I/O (macrocell 5) |
| Pin 7 | I/O β Bidirectional user I/O (macrocell 6) |
| Pin 8 | I/O β Bidirectional user I/O (macrocell 7) |
| Pin 9 | I/O β Bidirectional user I/O (macrocell 8) |
| Pin 10 | I/O β Bidirectional user I/O (macrocell 9) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β Bidirectional user I/O (macrocell 10) |
| Pin 13 | I/O β Bidirectional user I/O (macrocell 11) |
| Pin 14 | I/O β Bidirectional user I/O (macrocell 12) |
| Pin 15 | I/O β Bidirectional user I/O (macrocell 13) |
| Pin 16 | I/O β Bidirectional user I/O (macrocell 14) |
| Pin 17 | I/O β Bidirectional user I/O (macrocell 15) |
| Pin 18 | I/O β Bidirectional user I/O (macrocell 16) |
| Pin 19 | GND β Ground |
| Pin 20 | I/O β Bidirectional user I/O (macrocell 17) |
| Pin 21 | I/O β Bidirectional user I/O (macrocell 18) |
| Pin 22 | I/O β Bidirectional user I/O (macrocell 19) |
| Pin 23 | I/O β Bidirectional user I/O (macrocell 20) |
| Pin 24 | I/O β Bidirectional user I/O (macrocell 21) |
| Pin 25 | VCC β +5 V supply |
| Pin 26 | I/O β Bidirectional user I/O (macrocell 22) |
| Pin 27 | I/O β Bidirectional user I/O (macrocell 23) |
| Pin 28 | I/O β Bidirectional user I/O (macrocell 24) |
| Pin 29 | GND β Ground |
| Pin 30 | I/O β Bidirectional user I/O (macrocell 25) |
| Pin 31 | I/O β Bidirectional user I/O (macrocell 26) |
| Pin 32 | I/O β Bidirectional user I/O (macrocell 27) |
| Pin 33 | I/O β Bidirectional user I/O (macrocell 28) |
| Pin 34 | I/O β Bidirectional user I/O (macrocell 29) |
| Pin 35 | I/O β Bidirectional user I/O (macrocell 30) |
| Pin 36 | VCC β +5 V supply |
| Pin 37 | I/O β Bidirectional user I/O (macrocell 31) |
| Pin 38 | I/O β Bidirectional user I/O (macrocell 32) |
| Pin 39 | I/O β Bidirectional user I/O (macrocell 33) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β Bidirectional user I/O (macrocell 34) |
| Pin 42 | I/O β Bidirectional user I/O (macrocell 35) |
| Pin 43 | I/O β Bidirectional user I/O (macrocell 36) |
| Pin 44 | I/O β Bidirectional user I/O (macrocell 37) |
| Pin 45 | I/O β Bidirectional user I/O (macrocell 38) |
| Pin 46 | I/O β Bidirectional user I/O (macrocell 39) |
| Pin 47 | VCC β +5 V supply |
| Pin 48 | I/O β Bidirectional user I/O (macrocell 40) |
| Pin 49 | I/O β Bidirectional user I/O (macrocell 41) |
| Pin 50 | I/O β Bidirectional user I/O (macrocell 42) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β Bidirectional user I/O (macrocell 43) |
| Pin 53 | I/O β Bidirectional user I/O (macrocell 44) |
| Pin 54 | I/O β Bidirectional user I/O (macrocell 45) |
| Pin 55 | I/O β Bidirectional user I/O (macrocell 46) |
| Pin 56 | I/O β Bidirectional user I/O (macrocell 47) |
| Pin 57 | I/O β Bidirectional user I/O (macrocell 48) |
| Pin 58 | VCC β +5 V supply |
| Pin 59 | I/O β Bidirectional user I/O (macrocell 49) |
| Pin 60 | I/O β Bidirectional user I/O (macrocell 50) |
| Pin 61 | I/O β Bidirectional user I/O (macrocell 51) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β Bidirectional user I/O (macrocell 52) |
| Pin 64 | I/O β Bidirectional user I/O (macrocell 53) |
| Pin 65 | I/O β Bidirectional user I/O (macrocell 54) |
| Pin 66 | I/O β Bidirectional user I/O (macrocell 55) |
| Pin 67 | I/O β Bidirectional user I/O (macrocell 56) |
| Pin 68 | I/O β Bidirectional user I/O (macrocell 57) |
| Pin 69 | VCC β +5 V supply |
| Pin 70 | I/O β Bidirectional user I/O (macrocell 58) |
| Pin 71 | I/O β Bidirectional user I/O (macrocell 59) |
| Pin 72 | I/O β Bidirectional user I/O (macrocell 60) |
| Pin 73 | GND β Ground |
| Pin 74 | I/O β Bidirectional user I/O (macrocell 61) |
| Pin 75 | I/O β Bidirectional user I/O (macrocell 62) |
| Pin 76 | I/O β Bidirectional user I/O (macrocell 63) |
| Pin 77 | I/O β Bidirectional user I/O (macrocell 64) |
| Pin 78 | IN β Dedicated input 1 (global clock candidate) |
| Pin 79 | IN β Dedicated input 2 |
| Pin 80 | IN β Dedicated input 3 |
| Pin 81 | IN β Dedicated input 4 |
| Pin 82 | IN β Dedicated input 5 |
| Pin 83 | IN β Dedicated input 6 |
| Pin 84 | IN β Dedicated input 7 |
| Pin 85 | OE β Global output enable |
| Pin 86 | CLK β Global clock input |
| Pin 87 | CLR β Global clear / reset |
| Pin 88 | VCC β +5 V supply |
| Pin 89 | NC β Not connected (per datasheet) |
| Pin 90 | NC β Not connected (per datasheet) |
| Pin 91 | GND β Ground |
| Pin 92 | NC β Not connected (per datasheet) |
| Pin 93 | NC β Not connected (per datasheet) |
| Pin 94 | NC β Not connected (per datasheet) |
| Pin 95 | NC β Not connected (per datasheet) |
| Pin 96 | NC β Not connected (per datasheet) |
| Pin 97 | NC β Not connected (per datasheet) |
| Pin 98 | NC β Not connected (per datasheet) |
| Pin 99 | NC β Not connected (per datasheet) |
| Pin 100 | NC β Not connected (per datasheet) |
Typical Applications
EPM5192AQC-1 is suitable for 6 applications: Legacy ISA Bus Address Decoding, PC/104 Peripheral Glue Logic, Industrial Control State Machines, VME Bus Interface Logic, Replacement of 74LS / 74HC Discrete Logic, Test and Measurement Front-End Multiplexing.
Legacy ISA Bus Address Decoding
The EPM5192AQC-1 fits legacy ISA bus address decoding because its 192 macrocells and 64 I/O comfortably handle the full 24-bit address range plus wait-state and chip-select glue logic. The 40 ns tPD keeps decode-to-chip-select latency well under an ISA bus cycle (125 ns at 8 MHz), and 5 V Β±5 % supply tolerance matches the ISA rail exactly. The instant-on OTP configuration is preferred over SRAM-based FPGAs because the host CPU can begin boot ROM accesses in microseconds without waiting for bitstream loading.
Recommended
PC/104 Peripheral Glue Logic
The EPM5192AQC-1 is well suited to PC/104 peripheral boards where multiple 8- and 16-bit peripherals (UARTs, parallel ports, IDE interfaces, A/D converters) must be decoded, muxed, and interrupt-routed with deterministic timing. The 64 I/O pins are enough to break out all chip selects and strobes for a typical PC/104 stack, while 40 ns tPD comfortably handles 8 MHz PC/104 bus cycles. The PQFP-100 surface-mount footprint fits the PC/104 3.55-inch board height envelope and the 5 V supply matches the PC/104 rail directly without level translation.
Recommended
Industrial Control State Machines
The EPM5192AQC-1 suits industrial control state machines driving motor controllers, valve banks, and safety interlocks because its 192 macrocells hold substantial FSM graphs plus combinational glue, and the OTP configuration boots in microseconds at power-on for fail-safe startup. The 0 Β°C to 70 Β°C commercial temperature range covers most factory-floor enclosures, and the 5 V CMOS I/O directly drives 24 V industrial signal conditioning modules through optocouplers. The deterministic MAX 5000 interconnect eliminates the timing-variability concerns that arise with SRAM-based FPGAs in hard-real-time control loops.
Recommended
VME Bus Interface Logic
The EPM5192AQC-1 works in VME bus interface cards as the address-decoder, interrupt-acknowledge handler, and bus-timing glue. VMEbus runs at 5 V with up to 32-bit data and address cycles, and the part's 192 macrocells are enough to implement a full VME slave or master interface state machine. The 40 ns tPD easily meets VME's 80 ns minimum cycle time at 12.5 MHz, and the PQFP-100 footprint suits the 6U and 3U VME card mechanical envelope. Designers should verify bus-arbiter and DTACK timing margins using MAX+PLUS II timing simulation.
Recommended
Replacement of 74LS / 74HC Discrete Logic
The EPM5192AQC-1 can replace dozens of 74LS / 74HC glue-logic packages on a crowded board by collapsing address decoders, latches, muxes, and bus transceivers into a single 192-macrocell CPLD. With 64 I/O and 7 dedicated inputs, the device offers enough user pins to replace 8 to 12 octal SSI/MSI packages, reducing board area, BOM count, and assembly cost. The 40 ns propagation delay is comparable to 74LS (β 10 ns gate delay plus interconnect) and faster than 74HC at 5 V for most decode paths.
Recommended
Test and Measurement Front-End Multiplexing
The EPM5192AQC-1 fits test-and-measurement front-end designs that need to multiplex analog signals, switch gain ranges, and sequence relay drivers under deterministic timing. Its 192 macrocells handle scan-list state machines plus 64 channels of low-frequency switching logic, while 5 V CMOS I/O directly drives small-signal relays and analog switches without external buffers. The deterministic tPD simplifies test-cycle timing budgets, and the legacy MAX+PLUS II toolchain supports AHDL testbench generation for verification.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192AQC-1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192AQC | EPM5192AGC-15 | EPM5192AGC-20 | EPM5192AGC | EPM5192AJC-15 | EPM5192AJC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQFP-100 (0.635 mm pitch) | PQFP-100 (0.635 mm pitch) - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 | 192 |
| User I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Operating Temperature | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C |
| Configuration | OTP / UV-Erasable EPROM | OTP / UV-Erasable EPROM | OTP / UV-Erasable EPROM (windowed) | OTP / UV-Erasable EPROM (windowed) | OTP / UV-Erasable EPROM (windowed) | UV-Erasable EPROM | UV-Erasable EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster speed grade than the base EPM5192AQC (vs EPM5192AQC)
- 192 macrocells in PQFP-100 - highest-density MAX 5000 PQFP (vs EPM5130 and EPM5128 MAX 5000 PQFP-100 variants)
- Legacy 5 V OTP design with deterministic timing (vs Modern SRAM-based CPLDs (MAX II, MAX V, MAX 10))
Design Notes
Estimated: at 5 V VCC and 64 I/O switching at 25 MHz with 50 pF loads, the EPM5192AQC-1 draws approximately 250 to 400 mA from the 5 V rail during dynamic operation. Provide a 100 Β΅F tantalum bulk capacitor and a 0.1 Β΅F ceramic decoupling cap on each VCC pin (pins 25, 36, 47, 58, 69, 88 per datasheet recommended layout). Keep the VCC trace short and wide; separate analog and digital grounds if any analog circuitry shares the board.
Estimated: at 300 mA VCC current and 5 V supply, the EPM5192AQC-1 dissipates approximately 1.5 W. The PQFP-100 package has a typical theta_JA of 40 to 50 Β°C/W with still air on a 4-layer JEDEC test board, so junction temperature rise above ambient is approximately 60 to 75 Β°C. Within the 0 Β°C to 70 Β°C commercial range this is well within limits, but designers should avoid placing the part near hot components and should provide adequate copper pour on VCC/GND for heat spreading.
PQFP-100 with 0.635 mm lead pitch requires surface-mount assembly with fine-pitch soldering. Recommended footprint: 0.30 mm wide pads with 0.10 mm solder mask dams between adjacent pads. Use a JEDEC MSL-3 handling protocol (30 Β°C / 60 % RH floor life) since plastic PQFP packages absorb moisture. Reflow profile should follow JEDEC J-STD-020 with peak temperature not exceeding 220 Β°C for the SnPb variant or 245 Β°C for lead-free.
Common pitfalls: (1) connecting a 3.3 V logic signal to the EPM5192AQC-1's 5 V I/O without a level shifter - this can damage the input; the part is not 3.3 V-tolerant. (2) Forgetting that the JTAG/programming pins are shared with user I/O on some MAX 5000 configurations - check the pinout before assigning critical signals. (3) Assuming the part can be reprogrammed in-circuit - the OTP variants cannot, so generate the JEDEC map with the final design locked before committing to programming.
Decoupling: place a 0.1 Β΅F X7R ceramic capacitor within 3 mm of every VCC/GND pair on the PQFP-100 footprint. Route high-speed clock and output-enable signals on inner layers with a continuous ground reference plane. Use 45-degree bends on all I/O traces and avoid right-angle turns to minimize reflections on the faster -15 and -20 speed grades. Keep JTAG programming signals away from switching I/O to prevent programming noise coupling.
Compliance Information
EPM5192AQC-1 is a legacy 1990s-era PQFP-100 CPLD predating widespread RoHS compliance documentation. RoHS, REACH, lead-free, and halogen-free status were not specified in the verified distributor data and should be confirmed with the supplier's CoC for any new procurement. AEC-Q100 is not applicable (automotive qualification was never pursued for MAX 5000).
