EPM9320ALC84-20 vs EPM9320ALI84-10N Comparison
Detailed side-by-side comparison of EPM9320ALC84-20 by Altera and EPM9320ALI84-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-20 | EPM9320ALI84-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $21.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/Os | 212 | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Package | PLCC-84 | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Process Technology | 0.5 Β΅m CMOS EEPROM | CMOS EEPROM |
| Supply Voltage | 5.0 V | β |
| Programmability | In-system via IEEE 1149.1 JTAG | β |
| Operating Temperature | [DATA_NEEDED: commercial or industrial grade] | -40C to +85C (industrial) |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Memory | Non-volatile EEPROM | EEPROM, non-volatile |
| Boundary Scan | JTAG IEEE 1149.1 | β |
| Design Software | MAX+PLUS II / Quartus II (legacy) | β |
| RoHS Status | [DATA_NEEDED: per Altera datasheet] | β |
| Architecture | β | MAX (Multiple Array MatriX), 3rd generation |
| Usable Gates | β | 6,000 to 12,000 |
| User I/O Pins | β | 56 |
| Pin-to-Pin Delay | β | 10 ns |
| Maximum Counter Frequency | β | 144.9 MHz |
| VCCINT (Core Supply) | β | 5.0 V |
| VCCIO (I/O Supply) | β | 3.3 V or 5.0 V |
| Input Logic Levels | β | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | β | Yes (IEEE Std. 1149.1 JTAG) |