Altera

EPM9320ALI84-10N - 320-Macrocell 10ns MAX 9000 CPLD | Altera

MPN: EPM9320ALI84-10N ✗ End of Life

In Stock Ships in 1-3 business days

5.0 V Vdss 84-pin PLCC (J-lead, 1.270 mm pitch) Package 144.9 MHz Speed EEPROM, non-volatile Memory

From $21.95 USD / Unit

MOQ: 1 |

Price updated: 2026-09-13

Volume Pricing

Qty	Unit Price	Extended
1	$38.5	$38.50
10	$34.2	$342.00
100	$29.8	$2,980.00
500	$25.4	$12,700.00
1,000	$21.95	$21,950.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

EPM9320ALI84-10N Overview

The Altera EPM9320ALI84-10N is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 320 macrocells, 20 Logic Array Blocks (LABs), and 6,000 to 12,000 usable gates in a 5.0-V CMOS EEPROM-based architecture. Housed in an 84-pin PLCC (Plastic Leaded Chip Carrier) package with J-bend terminals on a 1.270 mm pitch, this device offers pin-to-pin delays as fast as 10 ns and counter speeds up to 144 MHz, making it suitable for high-performance glue-logic, bus-interface, and state-machine applications.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocells with a central interconnect matrix. In the system hierarchy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers deterministic 10 ns timing, instant-on EEPROM configuration, and high I/O count, but lacks the fine-grained LUT fabric of an FPGA. The MAX 9000 family implements Altera's third-generation Multiple Array MatriX (MAX) architecture, which groups macrocells into LABs joined by a programmable interconnect array (PIA), enabling predictable timing and efficient state-machine implementation.

Key features of the EPM9320ALI84-10N include 56 user I/O pins, separate VCCINT (5.0 V) and VCCIO pins for output-driver voltage selection (3.3 V or 5.0 V), and built-in IEEE Std. 1149.1 JTAG interface for in-system programmability (ISP). The device supports TTL-compatible inputs at 5.0-V VCCINT and offers multi-voltage I/O for mixed-voltage designs. Programmable power reduction modes lower quiescent current during standby, while the -10 speed grade delivers the fastest pin-to-pin delay in the MAX 9320 die family.

The MAX architecture uses EEPROM configuration memory, which provides non-volatile storage and infinite re-programmability without external boot devices. The 320 macrocells are split into 20 LABs of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O control. This organization is optimized for wide combinatorial and registered logic functions typical of address decoding, bus arbitration, and asynchronous state-machine designs.

Typical applications include high-performance bus-interface and address decoding in microprocessor systems, peripheral glue logic in telecom and networking equipment, industrial control and instrumentation logic, and replacement of multiple discrete TTL/CMOS MSI parts on legacy PCBs. The 84-pin PLCC package and through-hole-compatible socket footprint also make the EPM9320ALI84-10N a common choice for legacy industrial and military designs that require hand-reworkability.

When designing with the EPM9320ALI84-10N, ensure that VCCINT is always tied to 5.0 V, while VCCIO can be set to 3.3 V or 5.0 V depending on the I/O rail. Use the JTAG interface for in-system re-programmability and boundary-scan testing, and observe the maximum I/O current ratings per bank to avoid output-buffer overheating. The -10 speed grade has the highest dynamic ICC; for lower-power designs, consider the slower -12 or -15 grades in the same MAX 9320 die family.

This page synthesizes the manufacturer datasheet, current distributor stock levels, drop-in alternatives drawn from the same MAX 9000 family and competitor CPLD lines, and practical PCB design guidance not found in a single manufacturer document - information gain targeted at engineers maintaining or upgrading legacy 5 V MAX 9000 designs.

Drop-in alternatives for EPM9320ALI84-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPM9320ALI84-10N (same form factor and footprint) — differing in Package, Mounting Type, Supply Voltage (VCC), Process Technology, Usable Gates.

EPM9320ALC84-10

Intel

Package: 84-pin PLCC (J-Lead)

Mounting Type: Surface Mount / Through-Hole (PLCC socket)