10AX115H2F34I2SG - Arria 10 GX 1.15M Logic Elements FPGA | Altera | Intel
MPN: 10AX115H2F34I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4530 | $45,300.00 |
| 50 | $4220 | $211,000.00 |
| 100 | $3990 | $399,000.00 |
| 500 | $3640 | $1,820,000.00 |
Drop-in alternatives for 10AX115H2F34I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115H2F34I2LG
✅ Drop-In✓ In Stock
$4995 / Unit
View Datasheet →10AX115H2F34I1SG
✅ Drop-In✓ In Stock
$3700 / Unit
View Datasheet →10AX115H2F34E2SG
✅ Drop-In✓ In Stock
$5500 / Unit
View Datasheet →10AX115H2F34E2LG
✅ Drop-In✓ In Stock
$5950 / Unit
View Datasheet →10AX115H2F34E1SG
✅ Drop-In✓ In Stock
$3300 / Unit
View Datasheet →10AX115H1F34I1SG
✅ Drop-In✓ In Stock
$6500 / Unit
View Datasheet →10AX115H1F34E1SG
✅ Drop-In✓ In Stock
$2895 / Unit
View Datasheet →10AX115H2F34I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Adaptive Logic Modules (ALMs) | 427,200 |
| Embedded Memory | 68.86 Mbit |
| DSP Blocks | 1,518 (variable precision, hardened FP32) |
| Transceiver Channels | 24 (max up to 14.1 Gbps) |
| PCIe Hard IP | 2x PCIe Gen3 |
| Process Technology | 20 nm Tri-Gate |
| Core Voltage (SmartVID) | 0.85 V to 0.9 V |
| Speed Grade | H2 |
| Temperature Grade | Industrial (I2, -40C to +100C Tj) |
| Package | 1152-ball FC-FBGA (F34) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AX115H2F34I2SG Pin Configuration
| Pin B1 | REFCLK_p — Transceiver reference clock, bank L0 |
| Pin B2 | REFCLK_n — Transceiver reference clock complement, bank L0 |
| Pin AF14 | VCC — Core power supply (SmartVID 0.85-0.9 V) |
| Pin GND | VSS — Ground ball (multiple positions) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115H2F34I2SG is suitable for 6 applications: 4K/UHD Broadcast Video Processing, 5G NR Small-Cell Baseband Processing, Military & Aerospace Signal Processing, Test & Measurement Instrumentation, High-Performance Computing Accelerator Card, ASIC Prototyping & Emulation.
4K/UHD Broadcast Video Processing
The 10AX115H2F34I2SG is well-matched to 4K/UHD broadcast contribution encoders and IPTV media gateways. With 1,150,000 logic elements, 68.86 Mbit embedded memory, and 1,518 hardened floating-point DSP blocks (up to ~1.5 TFLOPs FP32), the FPGA can run real-time HEVC/H.265 4:2:2 10-bit encoding for multiple 4K streams without external ASIC co-processors. The integrated 14.1 Gbps transceivers support 12G-SDI, SMPTE 2022, and 10GbE network aggregation with deterministic latency. Placed as the central processing device alongside a TI LMK03328 clock conditioner and Micron DDR4 external memory, the 115 LE budget allows line-rate processing at UHD p60.
Recommended
5G NR Small-Cell Baseband Processing
The 10AX115H2F34I2SG is suitable for 5G NR small-cell and LTE-A baseband digital front-end designs. The 1.15M LE density supports full PHY-layer processing for 4T4R 100 MHz 5G NR small cells with LDPC/Polar encoding at sub-1 ms latency. The 24 transceiver channels at up to 14.1 Gbps handle CPRI 9.8 Gbps or eCPRI fronthaul, plus JEDEC JESD204B/C links to RF ADCs/DACs. The I2 industrial temperature grade supports outdoor sealed-enclosure deployments (-40C to +100C Tj). Pairing with a TI AFE7950 RF transceiver and Intel eASIC SoC host, the Arria 10 delivers PHY-layer density previously requiring ASICs.
Recommended
Military & Aerospace Signal Processing
The 10AX115H2F34I2SG is widely deployed in ruggedized MIL-spec signal-processing systems, including electronic-warfare receivers, radar preprocessing, and avionics video/graphics pipelines. The 20 nm Tri-Gate Arria 10 architecture provides radiation-tolerant latch-up immunity and SmartVID dynamic power scaling for thermal envelopes in conduction-cooled ATR enclosures. Industrial-grade I2 temperature and a 1152-ball FCBGA with controlled CTE substrate support MIL-STD-810 thermal cycling. Combined with the hardened IEEE 754 single-precision floating-point DSP, the device accelerates FFT, FIR, and matrix arithmetic without sacrificing precision in EW and SAR processing workloads.
Recommended
Test & Measurement Instrumentation
The 10AX115H2F34I2SG suits high-end test and measurement instruments, including arbitrary waveform generators, real-time oscilloscopes, and protocol analyzers. Its 1,518 hardened FP32 DSP blocks enable multi-GS/s arbitrary waveform synthesis with on-the-fly waveform mathematics, while the integrated 14.1 Gbps transceivers capture or drive PCIe Gen3, USB 3.1, SATA, and 10GbE data streams. The 68.86 Mbit embedded memory provides deep real-time sample buffers. Used alongside a TI ADC12DJ5200 RF ADC and an external DDR4 capture buffer, the FPGA delivers sample rates beyond 5 GS/s with deterministic trigger latency.
Recommended
High-Performance Computing Accelerator Card
The 10AX115H2F34I2SG is an effective PCIe Gen3 add-in-card accelerator for HPC workloads such as genomics, computational finance, and machine-learning inference. Two hardened PCIe Gen3 IP blocks support x8 endpoint configuration with bus-master DMA to host memory at >6 GB/s. The 1,518 hardened FP32 DSPs deliver >1 TFLOPs of single-precision throughput for HFT, FFT, and OpenCL kernels. With 1.15M LEs the FPGA supports substantial on-chip data-flow graphs without external co-processors. The industrial temperature grade fits rack-mounted server inlet air up to ~65C with appropriate airflow design.
Recommended
ASIC Prototyping & Emulation
The 10AX115H2F34I2SG is widely used as an ASIC prototyping platform, with multiple FPGAs commonly partitioned via dedicated multi-FPGA interconnect bridges. The 1.15M LE density provides enough logic capacity to map medium-complexity ASIC blocks (typically ~5-10M ASIC gates) into a single device for fast bring-up and software-development hardware. The industrial temperature grade supports prototype bring-up in thermally modest lab enclosures. Used alongside an Arria 10 SoC for control-plane services and external DDR4 emulation memory, it accelerates RTL validation and pre-silicon firmware development.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H2F34I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H2F34I2LG | 10AX115H2F34I1SG | 10AX115H2F34E2SG | 10AX115H2F34E2LG |
|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA (F34) | 1152-ball FC-FBGA (F34) - same | 1152-ball FC-FBGA (F34) - same | 1152-ball FC-FBGA (F34) - same | 1152-ball FC-FBGA (F34) - same |
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory | 68.86 Mbit | 68.86 Mbit | 68.86 Mbit | 68.86 Mbit | 68.86 Mbit |
| Speed Grade | H2 | H2 | H2 | H2 | H2 |
| Temperature Grade | Industrial I2 (-40C to +100C Tj) | Industrial I2 (-40C to +100C Tj) | Extended-industrial I1 (-40C to +125C Tj) | Extended E2 (0C to +100C Tj) | Extended E2 (0C to +100C Tj) |
| Transceiver Rate | 14.1 Gbps | 14.1 Gbps | 14.1 Gbps | 14.1 Gbps | 14.1 Gbps |
| RoHS / Lead-Free | Compliant / Yes | Compliant / Yes (LG suffix = Pb-free) | Compliant / Yes | Compliant / Yes | Compliant / Yes (LG suffix = Pb-free) |
| Process / Core Voltage | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID | 20 nm / 0.85-0.9 V SmartVID |
Key Differentiators
- Largest Arria 10 GX density (1.15M LE) in the F34 FCBGA (vs 10AX066H2F34I2SG)
- Integrated 14.1 Gbps transceivers with hardened PCIe Gen3 (vs 10AX115N3F40E2SG (non-GX variant))
- Hardened IEEE 754 single-precision floating-point DSP (vs Cyclone 10 GX FPGAs)
Design Notes
At typical Arria 10 GX 115 utilization (60-70% logic, full transceiver rate), worst-case power dissipation can reach 20-25 W. The 1152-ball FC-FBGA F34 package requires a high-performance thermal solution - 4-6 layer PCB with at least 1 oz copper and a heatsink with airflow of 1-2 m/s. Compute T_j_max using the SmartVID-specific thermal resistance from the Arria 10 GX Thermal Modeling User Guide. Always measure T_j in a populated system using the on-die temperature sensor via JTAG before final qualification.
PCB substrate for the 1152-ball FCBGA must be designed for >6 GHz Nyquist to support 14.1 Gbps transceiver operation. Use a low-loss dielectric (Megtron 6, Rogers RO4350B, or similar with Dk <3.5, Df <0.005 at 5 GHz). Stack-up must maintain 50 ohm single-ended and 90 ohm differential impedances for the transceiver channels with <0.5 dB/inch loss at 7 GHz. Reference the Arria 10 GX Transceiver Layout Guidelines for via pattern, length matching, and AC-coupling capacitor placement.
SmartVID requires a programmable PMIC such as the Intel Enpirion EM11x0 or equivalent with 10-20 mV VID step resolution. The VID bus (4 wires: VID0-VID3) connects from the configuration image source (typically an external SPI flash) to the PMIC. Bulk decoupling requires 22 uF + 0.1 uF ceramic + 470 uF polymer tantalum per VCC and VCCP rails. Verify transient response of the PMIC for >10 A/us load steps during dynamic reconfiguration - undershoot below 0.83 V can cause SmartVID undervoltage lockout.
Common pitfalls include (1) failing to disable unused transceivers via Quartus Prime configuration to save 1-2 W per channel, (2) using LVCMOS 1.8 V I/O standards without configuring the HPS_IO or general-purpose I/O bank voltage reference, which can damage I/O banks, (3) ignoring PCIe Gen3 link-training requirements - both 100 MHz and 125 MHz reference clocks must be clean and routed with 90 ohm differential impedance, and (4) forgetting to instantiate the JTAG IDCODE in the design, which prevents subsequent configuration via JTAG.
Compliance Information
RoHS and REACH compliant per Altera/Intel FPGA product environmental compliance documentation. AEC-Q100 not applicable (FPGA is not an automotive-qualified discrete). Lead-free across all variants. Conflict-minerals declaration per Intel supplier-responsibility policy.
