10AX115S1F45I1SG - Arria 10 GX FPGA, 1.15M LE, 1932-FCBGA | Intel
MPN: 10AX115S1F45I1SG β Active| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for 10AX115S1F45I1SG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115S1F45E1SG
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$5850 / Unit
View Datasheet β10AX115S1F45I2SG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AX115S2F45I1SG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AX115S1F45I3SG
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10AX115S3F45I1SG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AX115S1F45I1SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory Bits | 68,857,560 |
| DSP Blocks (18x19 Multipliers) | 1560 |
| Maximum User I/O | 624 |
| Max Transceiver Data Rate | 14.1 Gbps |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Package | 1932-ball FCBGA (F45), 1.0 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | Industrial (I1) |
| Speed Grade | I1 (industrial) |
| Hardened IP | PCIe Gen3, 10/40/100 GbE MAC, DDR4 memory controllers |
| RoHS / Lead-Free | RoHS compliant (SG suffix) |
| Supplier | Intel (formerly Altera) |
10AX115S1F45I1SG 1932-ball fcbga (f45), 1.0 mm pitch Pin Configuration Guide
Complete pinout information for 10AX115S1F45I1SG (1932-ball fcbga (f45), 1.0 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115S1F45I1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115S1F45I1SG is suitable for 6 applications: 100G Optical Transport Line Cards, Military Radar Baseband Processing, ASIC Prototyping and Emulation, Medical Imaging Accelerators, Broadcast Video Processing, High-Performance Industrial Computing.
100G Optical Transport Line Cards
The 10AX115S1F45I1SG fits 100G optical transport due to its 14.1 Gbps transceivers that aggregate into 100 GbE pipes via built-in hard MACs. With 1,150,000 logic elements and 1560 DSP 18x19 blocks, it forwards packets, performs OTN framer functions, and executes forward error correction at line rate. The I1 industrial temperature grade ensures operation in carrier-grade central offices where ambient temperatures are uncontrolled. Pin-compatible S2/S3 OPNs allow upward migration when more transceivers are needed for 200G/400G uplinks.
Recommended
Military Radar Baseband Processing
The 10AX115S1F45I1SG handles radar baseband DSP because its 1560 18x19 multipliers enable pulse-Doppler, MTI, and SAR compression on streaming ADC samples. Industrial temperature grade (I1) suits ground-mobile and naval platforms, and 68,857,560 embedded bits allow large windowing buffers to be co-located with arithmetic. Hardened DDR4 controllers feed post-processed tracks to the host CPU. Designers should reserve per-pin transceiver supplies for IF digitiser links and follow Intel's Arria 10 PCB layout guidelines for matched-length serial lanes.
Recommended
ASIC Prototyping and Emulation
For ASIC prototyping, the 10AX115S1F45I1SG supplies 1,150,000 logic elements to map large SoC RTL partitions, while its DDR4 hard controllers model external DRAM in real time. Engineers use multi-FPGA partitioning to prototype designs exceeding 2M ASIC gates, leveraging partial reconfiguration to iterate on sub-modules without full bitstream reloads. Hardened PCIe Gen3 and GbE MACs let the prototype talk to real peripherals, accelerating software bring-up. Choose industrial speed grade for prototypes destined for production validation chambers.
Recommended
Medical Imaging Accelerators
The 10AX115S1F45I1SG accelerates CT, MRI, and ultrasound reconstruction pipelines by running back-projection, beamforming, and denoising kernels across its 1560 DSP blocks. 68 Mbits of embedded memory hold filter coefficients and intermediate slices, reducing off-chip bandwidth. Industrial temperature grade (I1) supports imaging carts in unconditioned clinical spaces. Latency-critical feedback loops benefit from deterministic hard transceivers rather than soft SERDES. Verify IEC 60601 EMI margins during PCB bring-up.
Recommended
Broadcast Video Processing
Broadcast video processors leverage the 10AX115S1F45I1SG's 14.1 Gbps transceivers for SDI-over-IP (SMPTE 2110) and 4K/8K mezzanine compression. 624 user I/Os drive HDMI/SDI companion chips, while 1560 DSP blocks accelerate deinterlacing and HDR tone-mapping in real time. Hardened 10/40/100 GbE MACs deliver uncompressed 4K streams to broadcast routers. Industrial temperature grade suits outside-broadcast trucks and master-control racks with limited climate control.
Recommended
High-Performance Industrial Computing
Industrial line cards route high-speed fabric traffic using the 10AX115S1F45I1SG's 14.1 Gbps transceivers for backplane connectivity and PCIe Gen3 endpoints for CPU attachment. With 68 Mbits of on-chip memory, packet headers and queuing metadata stay on-die, reducing external memory accesses. Industrial temperature grade (I1) meets harsh-environment requirements of factory automation and energy substation controllers. The 1932-ball FCBGA exposes enough I/O for parallel legacy interfaces alongside serial links, simplifying hybrid industrial designs.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115S1F45I1SG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115S1F45E1SG | 10AX115S1F45I2SG | 10AX115S2F45I1SG | 10AX115S1F45I3SG | 10AX115S3F45I1SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1932-ball FCBGA (F45), 1.0 mm pitch | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Speed Grade | I1 (industrial) | E1 (commercial) | I2 (industrial, faster) | I1 (industrial) | I3 (industrial, fastest) | I1 (industrial) |
| Transceiver Configuration | S1 | S1 | S1 | S2 (more transceivers) | S1 | S3 (more transceivers) |
| Embedded Memory Bits | 68,857,560 | 68,857,560 | 68,857,560 | 68,857,560 | 68,857,560 | 68,857,560 |
| DSP Blocks (18x19) | 1560 | 1560 | 1560 | 1560 | 1560 | 1560 |
| RoHS / Lead-Free | RoHS compliant (SG) | RoHS compliant (SG) | RoHS compliant (SG) | RoHS compliant (SG) | RoHS compliant (SG) | RoHS compliant (SG) |
Key Differentiators
- Industrial speed grade in the F45 package (vs 10AX115S1F45E1SG)
- Lower-cost entry to the Arria 10 S1 transceiver configuration (vs 10AX115S2F45I1SG)
- Faster upgrade path on the same PCB (vs 10AX115S1F45I2SG)
Design Notes
The 1932-ball F45 FCBGA at 1.0 mm pitch requires an HDI PCB stack-up with microvia escape and matched-length serial lanes. Follow Intel's Arria 10 layout guidelines: dedicated transceiver reference clock planes, isolation of analog supplies from digital switching, and 4-6 decoupling capacitors per power pin (0.1 uF, 1 uF, 10 uF mix). Stack-up should target 1 oz copper on outer layers and 0.5 oz on inner layers with a low-loss dielectric for 14.1 Gbps signals. Estimated: at full transceiver utilisation the part dissipates roughly 25-35 W, so the PCB thermal solution should include thermal vias to internal copper planes.
Estimated: Arria 10 devices in the F45 FCBGA typically dissipate 15-40 W depending on transceiver utilisation and toggle rate. With industrial temperature grade (I1), junction temperature must stay below 100 C. Use thermal vias under the central ball array and a heatsink with thermal interface material rated for the application environment. Always validate via a thermal simulation using actual activity factors; per-pin power data is in the Arria 10 PowerPlay Early Power Estimator.
Do not confuse SX/GX OPNs with NX OPNs - they share the same package but NX variants replace transceivers with general-purpose I/O. Pin assignments for the S1 transceiver configuration differ from S2/S3, so swapping OPNs without re-fitting the bitstream will cause configuration failure. Always specify the exact OPN in the BOM and validate the configured device ID via JTAG before production release. The 'ES' suffix denotes engineering samples - never ship ES parts to production without FA qualification.
Compliance Information
RoHS compliance indicated by 'SG' suffix in the OPN per Intel ordering part number conventions. AEC-Q100 not applicable - FPGAs are not AEC-Q100 qualified; industrial temperature grade (I1) is the relevant environmental rating.
