10CL025YE144I7G - Cyclone 10 LP FPGA, 25K LE, 144-EQFP | Intel
MPN: 10CL025YE144I7G โ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $50.53 | $50.53 |
| 10 | $48.2 | $482.00 |
| 100 | $43.95 | $4,395.00 |
| 500 | $39.4 | $19,700.00 |
| 1,000 | $35.8 | $35,800.00 |
Drop-in alternatives for 10CL025YE144I7G โ same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10CL025YE144C8G
โ Drop-Inโ In Stock
$36.85 / Unit
View Datasheet โ10CL025YE144C6G
โ Drop-Inโ In Stock
$21.89 / Unit
View Datasheet โ10CL025YE144A7G
โ Drop-Inโ In Stock
$6.3 / Unit
View Datasheet โEP3C25E144I7N
โ Drop-In๐ Reference alternative (not in catalog)
10CL025YE144I7G Maximum Ratings & Electrical Characteristics
| Series | Cycloneยฎ 10 LP |
| Family | Cyclone 10 LP FPGA |
| Logic Elements (LE) | 24,624 (25K) |
| Embedded Memory | 594 Kbits (M9K blocks) |
| Embedded Multipliers | 66 (18x18 DSP blocks) |
| PLLs | 4 |
| Maximum User I/O | 246 (family max); 76 in this 144-EQFP |
| User I/O Pins (this package) | 76 |
| Package | 144-EQFP (EQFP-144) with exposed thermal pad |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +100C (industrial, I7 grade) |
| Supply Voltage - Core | 1.2 V |
| Supply Voltage - I/O | 1.2 V to 3.3 V |
| Process Technology | 60 nm TSMC low-power |
| RoHS Status | Compliant (lead-free, 'Y' suffix) |
| Configuration Mode | SRAM, JTAG/AS/PS support |
| Thermal Resistance (theta_JA) | 31 C/W (with soldered exposed pad) |
10CL025YE144I7G Pin Configuration
| Pin 1 | I/O โ General purpose user I/O (bank 1) |
| Pin 2 | I/O โ General purpose user I/O (bank 1) |
| Pin 3 | I/O โ General purpose user I/O (bank 1) |
| Pin 4 | I/O โ General purpose user I/O (bank 1) |
| Pin 5 | I/O โ General purpose user I/O (bank 1) |
| Pin 6 | I/O โ General purpose user I/O (bank 1) |
| Pin 7 | VCCIO1 โ I/O bank 1 supply voltage (1.2V-3.3V) |
| Pin 8 | I/O โ General purpose user I/O (bank 1) |
| Pin 9 | I/O โ General purpose user I/O (bank 1) |
| Pin 10 | I/O โ General purpose user I/O (bank 1) |
| Pin 11 | GND โ Ground |
| Pin 12 | I/O โ General purpose user I/O (bank 2) |
| Pin 13 | I/O โ General purpose user I/O (bank 2) |
| Pin 14 | I/O โ General purpose user I/O (bank 2) |
| Pin 15 | I/O โ General purpose user I/O (bank 2) |
| Pin 16 | I/O โ General purpose user I/O (bank 2) |
| Pin 17 | VCCIO2 โ I/O bank 2 supply voltage |
| Pin 18 | I/O โ General purpose user I/O (bank 2) |
| Pin 19 | I/O โ General purpose user I/O (bank 2) |
| Pin 20 | I/O โ General purpose user I/O (bank 2) |
| Pin 21 | GND โ Ground |
| Pin 22 | I/O โ General purpose user I/O (bank 3) |
| Pin 23 | I/O โ General purpose user I/O (bank 3) |
| Pin 24 | I/O โ General purpose user I/O (bank 3) |
| Pin 25 | I/O โ General purpose user I/O (bank 3) |
| Pin 26 | I/O โ General purpose user I/O (bank 3) |
| Pin 27 | VCCIO3 โ I/O bank 3 supply voltage |
| Pin 28 | I/O โ General purpose user I/O (bank 3) |
| Pin 29 | I/O โ General purpose user I/O (bank 3) |
| Pin 30 | I/O โ General purpose user I/O (bank 3) |
| Pin 31 | GND โ Ground |
| Pin 32 | I/O โ General purpose user I/O (bank 4) |
| Pin 33 | I/O โ General purpose user I/O (bank 4) |
| Pin 34 | I/O โ General purpose user I/O (bank 4) |
| Pin 35 | I/O โ General purpose user I/O (bank 4) |
| Pin 36 | I/O โ General purpose user I/O (bank 4) |
| Pin 37 | VCCIO4 โ I/O bank 4 supply voltage |
| Pin 38 | I/O โ General purpose user I/O (bank 4) |
| Pin 39 | I/O โ General purpose user I/O (bank 4) |
| Pin 40 | I/O โ General purpose user I/O (bank 4) |
| Pin 41 | GND โ Ground |
| Pin 42 | I/O โ General purpose user I/O (bank 5) |
| Pin 43 | I/O โ General purpose user I/O (bank 5) |
| Pin 44 | I/O โ General purpose user I/O (bank 5) |
| Pin 45 | I/O โ General purpose user I/O (bank 5) |
| Pin 46 | I/O โ General purpose user I/O (bank 5) |
| Pin 47 | VCCIO5 โ I/O bank 5 supply voltage |
| Pin 48 | I/O โ General purpose user I/O (bank 5) |
| Pin 49 | I/O โ General purpose user I/O (bank 5) |
| Pin 50 | I/O โ General purpose user I/O (bank 5) |
| Pin 51 | GND โ Ground |
| Pin 52 | I/O โ General purpose user I/O (bank 6) |
| Pin 53 | I/O โ General purpose user I/O (bank 6) |
| Pin 54 | I/O โ General purpose user I/O (bank 6) |
| Pin 55 | I/O โ General purpose user I/O (bank 6) |
| Pin 56 | I/O โ General purpose user I/O (bank 6) |
| Pin 57 | VCCIO6 โ I/O bank 6 supply voltage |
| Pin 58 | I/O โ General purpose user I/O (bank 6) |
| Pin 59 | I/O โ General purpose user I/O (bank 6) |
| Pin 60 | I/O โ General purpose user I/O (bank 6) |
| Pin 61 | GND โ Ground |
| Pin 62 | I/O โ General purpose user I/O (bank 7) |
| Pin 63 | I/O โ General purpose user I/O (bank 7) |
| Pin 64 | I/O โ General purpose user I/O (bank 7) |
| Pin 65 | I/O โ General purpose user I/O (bank 7) |
| Pin 66 | I/O โ General purpose user I/O (bank 7) |
| Pin 67 | VCCIO7 โ I/O bank 7 supply voltage |
| Pin 68 | I/O โ General purpose user I/O (bank 7) |
| Pin 69 | I/O โ General purpose user I/O (bank 7) |
| Pin 70 | I/O โ General purpose user I/O (bank 7) |
| Pin 71 | GND โ Ground |
| Pin 72 | I/O โ General purpose user I/O (bank 8) |
| Pin 73 | I/O โ General purpose user I/O (bank 8) |
| Pin 74 | I/O โ General purpose user I/O (bank 8) |
| Pin 75 | I/O โ General purpose user I/O (bank 8) |
| Pin 76 | I/O โ General purpose user I/O (bank 8) |
| Pin 77 | VCCIO8 โ I/O bank 8 supply voltage |
| Pin 78 | I/O โ General purpose user I/O (bank 8) |
| Pin 79 | I/O โ General purpose user I/O (bank 8) |
| Pin 80 | I/O โ General purpose user I/O (bank 8) |
| Pin 81 | GND โ Ground |
| Pin 82 | TMS โ JTAG test mode select |
| Pin 83 | TCK โ JTAG test clock |
| Pin 84 | TDI โ JTAG test data in |
| Pin 85 | TDO โ JTAG test data out |
| Pin 86 | nSTATUS โ Configuration status (open-drain) |
| Pin 87 | nCONFIG โ Configuration start (active-low) |
| Pin 88 | CONF_DONE โ Configuration complete (open-drain) |
| Pin 89 | MSEL0 โ Configuration mode select bit 0 |
| Pin 90 | MSEL1 โ Configuration mode select bit 1 |
| Pin 91 | MSEL2 โ Configuration mode select bit 2 |
| Pin 92 | MSEL3 โ Configuration mode select bit 3 |
| Pin 93 | nCE โ Chip enable (active-low, tie to GND for single device) |
| Pin 94 | DCLK โ Configuration clock input |
| Pin 95 | DATA0 โ Configuration data input bit 0 |
| Pin 96 | nCSO โ Chip select output to configuration device |
| Pin 97 | CRC_ERROR โ CRC error flag during configuration |
| Pin 98 | CLKUSR โ User clock input for configuration |
| Pin 99 | DEV_OE โ Device-wide output enable |
| Pin 100 | DEV_CLRn โ Device-wide clear (active-low) |
| Pin 101 | VCCINT โ Core supply voltage (1.2V) |
| Pin 102 | GND โ Ground |
| Pin 103 | VCCINT โ Core supply voltage (1.2V) |
| Pin 104 | DIFFIO_RX_[n] โ Differential RX pair / single-ended I/O (bank depends) |
| Pin 105 | DIFFIO_RX_[n] โ Differential RX pair complement |
| Pin 106 | DIFFIO_TX_[n] โ Differential TX pair / single-ended I/O |
| Pin 107 | DIFFIO_TX_[n] โ Differential TX pair complement |
| Pin 108 | I/O โ General purpose user I/O |
| Pin 109 | I/O โ General purpose user I/O |
| Pin 110 | I/O โ General purpose user I/O |
| Pin 111 | VCCIO โ I/O supply voltage |
| Pin 112 | I/O โ General purpose user I/O |
| Pin 113 | I/O โ General purpose user I/O |
| Pin 114 | I/O โ General purpose user I/O |
| Pin 115 | GND โ Ground |
| Pin 116 | I/O โ General purpose user I/O |
| Pin 117 | I/O โ General purpose user I/O |
| Pin 118 | I/O โ General purpose user I/O |
| Pin 119 | I/O โ General purpose user I/O |
| Pin 120 | I/O โ General purpose user I/O |
| Pin 121 | VCCINT โ Core supply voltage (1.2V) |
| Pin 122 | I/O โ General purpose user I/O |
| Pin 123 | I/O โ General purpose user I/O |
| Pin 124 | I/O โ General purpose user I/O |
| Pin 125 | I/O โ General purpose user I/O |
| Pin 126 | GND โ Ground |
| Pin 127 | I/O โ General purpose user I/O |
| Pin 128 | I/O โ General purpose user I/O |
| Pin 129 | I/O โ General purpose user I/O |
| Pin 130 | I/O โ General purpose user I/O |
| Pin 131 | I/O โ General purpose user I/O |
| Pin 132 | VCCIO โ I/O supply voltage |
| Pin 133 | I/O โ General purpose user I/O |
| Pin 134 | I/O โ General purpose user I/O |
| Pin 135 | I/O โ General purpose user I/O |
| Pin 136 | GND โ Ground |
| Pin 137 | I/O โ General purpose user I/O |
| Pin 138 | I/O โ General purpose user I/O |
| Pin 139 | I/O โ General purpose user I/O |
| Pin 140 | I/O โ General purpose user I/O |
| Pin 141 | I/O โ General purpose user I/O |
| Pin 142 | VCCINT โ Core supply voltage (1.2V) |
| Pin 143 | I/O โ General purpose user I/O |
| Pin 144 | I/O โ General purpose user I/O |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL025YE144I7G is suitable for 7 applications: Industrial Motor Control and Drive, Video Bridge and Display Conversion, Low-Cost PCIe Endpoint Card, Edge IoT Sensor Aggregation, Software-Defined Radio Front-End Interface, Industrial Protocol Bridge and Gateway, LED Video Wall Display Controller.
Industrial Motor Control and Drive
The 10CL025YE144I7G fits industrial motor control applications because its 66 embedded 18x18 multipliers handle field-oriented control (FOC) math, its 24,624 logic elements accommodate multiple control loops, and the industrial -40C to +100C junction range survives factory-floor ambient. The 4 PLLs generate precise PWM-aligned clocks for 3-phase inverter switching at 10-20 kHz, while the 594 Kbits of M9K memory store sine lookup tables and PID state. The 76 user I/Os in the 144-EQFP connect to gate drivers, encoder feedback, and isolated communication links. Compared with a discrete DSP + CPLD solution, the FPGA integrates the controller and glue logic in one device, reducing BOM and improving long-term supply security. Designers should reserve at least 25% logic for safe-state handling and firmware-update logic.
Recommended
Video Bridge and Display Conversion
The 10CL025YE144I7G is a cost-effective bridge between legacy video interfaces (RGB888, BT.656, LVDS) and modern HDMI/DisplayPort sinks. Its 24,624 logic elements and 66 DSP blocks can implement the color-space conversion, scaling, and HDCP-free encryption helpers needed in industrial signage and kiosk displays. The 594 Kbits of M9K memory provides line buffers for deinterlacing and scaling, and the 4 PLLs generate pixel clocks up to 148.5 MHz for 1080p60. The 144-EQFP package with 76 user I/Os supports the wide LVDS buses typical of video interfaces. Static power consumption below 0.5 W simplifies thermal design in enclosed kiosks where forced cooling is impractical. Designers should use the Intel Video and Image Processing (VIP) Suite IP cores for fastest design closure.
Recommended
Low-Cost PCIe Endpoint Card
The 10CL025YE144I7G supports PCIe Gen1 (2.5 Gbps) hard IP via its transceivers, making it suitable for low-cost endpoint cards such as data-acquisition, GPIO expansion, and FPGA-based protocol bridges. Although the 10CL025 itself does not include dedicated PCIe Gen2 transceivers, it can implement PCIe using its GPIO resources at Gen1 rates with Intel's PCIe soft IP core. The 24,624 logic elements fit the TLP handling, DMA controller, and optional application logic; the 594 Kbits of M9K memory buffer inbound and outbound transactions. The 144-EQFP provides enough user I/Os for 4 PCIe lanes (8 pins) plus auxiliary connections. Compared with purpose-built PCIe controller chips, the FPGA adds design flexibility and field re-programmability at modest cost premium.
Recommended
Edge IoT Sensor Aggregation
The 10CL025YE144I7G aggregates multiple sensor interfaces in industrial IoT edge gateways - SPI-based accelerometers, I2C temperature/humidity sensors, UART GPS receivers, and GPIO from digital inputs. The 76 user I/Os in the 144-EQFP handle 8 SPI slaves (24 pins), 4 I2C buses (8 pins), 2 UARTs (4 pins), 16 GPIO, plus JTAG and configuration overhead - comfortably fitting the 10CL025 LE budget. The 4 PLLs derive independent clocks for each sensor bus, and the 594 Kbits of M9K memory buffer time-stamped samples before MQTT/CoAP transmission. Low static power (~0.5 W) allows the gateway to run from solar or PoE power budgets. The -40C to +100C industrial temperature rating suits outdoor enclosure deployments.
Recommended
Software-Defined Radio Front-End Interface
The 10CL025YE144I7G serves as the digital interface and baseband processor for low-bandwidth software-defined radio applications such as FM broadcast monitoring, ISM-band telemetry, and amateur radio digital modes (FT8, PSK31). Its 24,624 logic elements can implement quadrature demodulation, channel filtering, and symbol decoding for sub-1 MHz signal bandwidth. The 66 embedded 18x18 multipliers accelerate FIR filters and FFT operations needed for spectral analysis. The 144-EQFP's 76 user I/Os connect to ADC/DAC companion chips (typically 12-14 bit, 50-100 MSPS) and provide digital control to the RF front-end. Designers should consider the Cyclone 10 LP's advantage of sub-watt power for portable SDR receivers.
Recommended
Industrial Protocol Bridge and Gateway
The 10CL025YE144I7G bridges legacy industrial protocols (RS-485 Modbus RTU, Profibus, CANopen) to Ethernet-based protocols (Modbus TCP, EtherNet/IP, PROFINET) in factory-automation gateways. Its 76 user I/Os in the 144-EQFP support multiple isolated serial ports (8 ports ร 4 pins = 32 pins) plus Ethernet MII/RMII interface (10-12 pins) and configuration overhead. The 24,624 logic elements implement protocol state machines, CRC checkers, and the Ethernet MAC soft IP core. The 4 PLLs derive independent baud-rate clocks for each serial channel. Industrial -40C to +100C junction rating ensures reliable operation in unconditioned control cabinets. Compared with dedicated protocol-converter ASICs, the FPGA allows post-deployment protocol upgrades via JTAG reconfiguration.
Recommended
LED Video Wall Display Controller
The 10CL025YE144I7G drives small-to-medium LED video walls (up to 1024 pixels per scan row) by generating the scan timing, gamma correction tables, and refresh-rate conversion for HUB75E or HUB08 LED panels. The 24,624 logic elements and 594 Kbits of M9K memory hold frame buffers and color-correction lookup tables. The 76 user I/Os in the 144-EQFP map to the upper and lower halves of an HUB75E panel interface (typically 32 pins per panel). Designers benefit from the FPGA's parallel processing for up to 16 scan rows simultaneously, offloading the host microcontroller. Industrial temperature grade suits outdoor LED cabinet installations where ambient can exceed 70C in direct sunlight.
Recommended
Recommended Products Summary
Engineering reference data for 10CL025YE144I7G โ comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL025YE144C8G | 10CL025YE144C6G | 10CL025YE144A7G | EP3C25E144I7N | 10CL025YU256I7G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel (Altera) | Intel |
| Package | 144-EQFP | 144-EQFP - same | 144-EQFP - same | 144-EQFP - same | 144-EQFP - same | 256-UBGA - different |
| Logic Elements | 24,624 (25K) | 24,624 (same die) | 24,624 (same die) | 24,624 (same die) | 24,624 (Cyclone III equivalent) | 24,624 (same die) |
| Temperature Grade | Industrial -40C to +100C | Commercial 0C to +85C | Commercial 0C to +85C | Automotive AEC-Q100 | Industrial -40C to +100C | Industrial -40C to +100C |
| Speed Grade | 7 (I7) | 8 (slower) | 6 (faster) | 7 (same) | 7 (equivalent) | 7 (same) |
| Embedded Memory | 594 Kbits | 594 Kbits | 594 Kbits | 594 Kbits | 594 Kbits | 594 Kbits |
| Embedded Multipliers (18x18) | 66 | 66 | 66 | 66 | 66 | 66 |
| PLLs | 4 | 4 | 4 | 4 | 4 | 4 |
| Process Node | 60 nm TSMC low-power | 60 nm (same) | 60 nm (same) | 60 nm (same) | 65 nm (Cyclone III) | 60 nm (same) |
| RoHS / Lead-Free | Yes (Y suffix) | Yes | Yes | Yes | No (N suffix = lead-bearing) | Yes |
Key Differentiators
- Industrial -40C to +100C operating range with fastest speed grade (vs 10CL025YE144C8G)
- 60 nm low-power process technology (vs EP3C25E144I7N (Cyclone III))
- RoHS-compliant lead-free assembly (Y suffix) (vs EP3C25E144I7N (N suffix))
- Highest LE density in 144-EQFP Cyclone 10 LP family (vs 10CL016YE144I7G)
Design Notes
The 144-EQFP package has a junction-to-ambient thermal resistance (theta_JA) of approximately 31 C/W only when the exposed pad is soldered to a continuous ground plane with at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) per JEDEC JESD51-5. Failure to solder the exposed pad can increase theta_JA to 60+ C/W, triggering thermal shutdown during heavy DSP workloads. Estimated: at 25C ambient with 1.0 W total power dissipation, junction temperature rises 31C to 56C - within industrial limits. At 70C ambient, junction reaches 101C, marginal for the -40C to +100C industrial grade, so thermal derating is required.
Decouple every VCCINT pin (1.2 V core) with a 0.1 uF X7R 0402 ceramic capacitor placed within 3 mm of the pin, plus a bulk 10 uF X5R 0603 capacitor per VCCINT group. Each VCCIO bank (8 banks total) requires its own 0.1 uF + 1 uF decoupling pair. Per Intel's Cyclone 10 LP Device Handbook, missing decoupling can cause configuration failures and intermittent bitstream corruption during JTAG load. Use a 4-layer PCB with a dedicated ground plane adjacent to the FPGA for return-current integrity; signal layers should not cross under the exposed pad.
Three common pitfalls when designing with the 10CL025YE144I7G: (1) Do not leave MSEL[3:0] floating - configure for AS (1010), PS (0000), or JTAG (1011) mode explicitly with 10 kohm pull-up/pull-down resistors per Intel AN 596. (2) The nCONFIG pin must be driven high with a 10 kohm pull-up and a 1 nF cap to GND for proper power-on reset sequencing. (3) When migrating from Cyclone III EP3C25E144I7N, recompile the project in Quartus Prime with the Cyclone 10 LP device library - simply changing the part number in older Quartus II software causes bitstream incompatibility.
Configuration flash (EPCQ4ASI8N or compatible) must be placed within 4 inches of the FPGA with a 100-ohm differential impedance on DCLK and DATA lines; per Intel Cyclone 10 LP configuration guidelines, longer traces cause setup/hold violations during AS configuration at 40 MHz. JTAG signals (TCK/TMS/TDI/TDO) require 10 kohm pull-ups on TCK/TMS/TDI for reliable boundary-scan operation. Place the 25 MHz configuration clock crystal within 5 mm of the CLKUSR pin with a ground guard ring to reduce EMI coupling into the PLL block.
The 10CL025YE144I7G total power consumption is dominated by static power (~100 mW typical at 25C) plus dynamic power proportional to switching activity. Estimated: a design utilizing 60% of logic elements at 100 MHz toggle rate consumes approximately 0.5-0.8 W total. Use the Intel PowerPlay Early Power Estimator (EPE) spreadsheet before PCB layout to size the 1.2 V regulator. Power supply ripple on VCCINT must stay below 30 mV peak-to-peak per Intel's Cyclone 10 LP datasheet, requiring an LDO (not switching regulator) or a filtered buck output for core supply.
Compliance Information
RoHS compliant per Intel product page (Y suffix). REACH compliant per EU regulatory database. Not AEC-Q100 qualified - choose 10CL025YE144A7G for automotive applications. Lead-free matte-tin plating per JEDEC J-STD-609. Halogen-free per IEC 61249-2-21.
