10CX085YF672E6G - Cyclone 10 GX FPGA, 85K LE, 672-BGA | Intel
MPN: 10CX085YF672E6G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $382.5 | $3,825.00 |
| 100 | $340 | $34,000.00 |
| 250 | $306 | $76,500.00 |
| 500 | $280.5 | $140,250.00 |
Drop-in alternatives for 10CX085YF672E6G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10CX085YF672E5G
✅ Drop-In✓ In Stock
$289 / Unit
View Datasheet →10CX085YF672E6G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 GX |
| Logic Elements (LE) | 85,000 |
| Adaptive Logic Modules (ALM) | 31,000 |
| Embedded Memory | 5,959,680 bits (5.68 Mbit) |
| DSP Blocks | 216 |
| Maximum User I/O | 192 |
| Package | 672-BGA (FBGA, F672) |
| Process Node | 20 nm |
| Core Voltage (Vcc) | 0.85 V to 0.95 V |
| Operating Temperature | 0 C to +100 C |
| Speed Grade | -6 (commercial, fast) |
| Mounting Type | Surface Mount |
| Hard Memory Controllers | DDR3/DDR4 up to 1866 Mbps |
| Hard PCIe IP | PCIe Gen2 / Gen3 (hard IP) |
| Transceivers | Up to 12.5 Gbps |
| RoHS Status | Compliant |
10CX085YF672E6G 672-bga (fbga, f672) Pin Configuration Guide
Complete pinout information for 10CX085YF672E6G (672-bga (fbga, f672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX085YF672E6G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX085YF672E6G is suitable for 6 applications: Industrial Machine Vision, PCIe Gen3 Add-in Cards, Motor Control and Factory Automation, Broadcast Video Processing, Wireless Backhaul Baseband Preprocessing, Protocol Bridge and Industrial IoT Gateway.
Industrial Machine Vision
The 10CX085YF672E6G fits industrial machine vision pipelines because it integrates 5.68 Mbit of embedded SRAM for line buffering, 216 DSP blocks for Bayer-to-YUV conversion and Sobel edge detection, and 12.5 Gbps transceivers for uncompressed CoaXPress or fiber output. Placed between a high-speed image sensor and a host processor, the Cyclone 10 GX handles pixel-rate preprocessing at sustained >300 MPixels/s while keeping the host CPU free for inspection logic. Designers benefit from hard PCIe Gen3 IP when bridging to an x86 vision controller, and from hardened DDR3/DDR4 controllers that interface to external frame buffers with ECC for factory-floor reliability.
Recommended
PCIe Gen3 Add-in Cards
The 10CX085YF672E6G's hardened PCIe Gen2/Gen3 controller makes it a natural fit for low-cost PCIe add-in cards, including protocol analyzers, NVMe accelerator bridges, and FPGA-based data-acquisition cards. Unlike soft PCIe IP that consumes fabric and routing resources, the hard IP block frees logic for user application while supporting x1/x2/x4 link widths at 8 GT/s. The 672-BGA F672 package supports the transceivers required for the PCIe lane plus auxiliary serial links, and Intel's Quartus Prime provides reference designs that shorten time-to-prototype.
Recommended
Motor Control and Factory Automation
The 10CX085YF672E6G supports multi-axis motor control by combining 216 DSP blocks for field-oriented control (FOC) math, deterministic ALM fabric for state machines, and fast transceivers for EtherCAT or SERCOS feedback networks. Operating across 0 to +100 C industrial temperature range, it handles encoder decoding, current-loop PI control, and PWM generation for 3-phase inverters on a single die. Compared with DSP+MCU solutions, the FPGA delivers deterministic latency and parallel execution, simplifying safe-torque-off and STO implementations for IEC 61800 functional safety architectures.
Recommended
Broadcast Video Processing
The 10CX085YF672E6G suits broadcast video processing such as quad-SDI multiviewers, HDR-to-SDR converters, and frame-rate conversion. Its 5.68 Mbit embedded memory accommodates line/field buffers for 3G-SDI processing, and 12.5 Gbps transceivers natively handle SDI rates up to 6 Gbps (UHD-1) without external reclockers. The 192 user I/Os expose GPIOs for front-panel control and I2C/SPI housekeeping, while hard PCIe provides a path to upstream software for closed-caption extraction or audio embedding.
Recommended
Wireless Backhaul Baseband Preprocessing
In small-cell and outdoor-unit wireless backhaul designs, the 10CX085YF672E6G pre-processes IQ samples between RF transceivers and a host baseband ASIC. The 216 DSP blocks run crest-factor reduction (CFR) and digital pre-distortion (DPD) at LTE/5G NR channel bandwidths, while 12.5 Gbps transceivers interface to common RF ADC/DAC parts like the AD9361 family. Compared with ASSP baseband chips, the FPGA offers reconfigurable modulation support and field-upgradable algorithms, which is valuable for evolving 5G NR features.
Recommended
Protocol Bridge and Industrial IoT Gateway
The 10CX085YF672E6G works as a multi-protocol industrial gateway, bridging PROFINET, EtherCAT, Modbus TCP, and OPC UA traffic on a single fabric. Its combination of ALM-based deterministic logic and hard Ethernet MAC blocks (via external PHY) supports real-time traffic shaping, while the DDR3/DDR4 controllers back large packet buffers. Industrial temperature grade (0 C to +100 C) and a long-life Intel roadmap make it appropriate for factory-floor gateways expected to run for 10+ years.
Recommended
Recommended Products Summary
Engineering reference data for 10CX085YF672E6G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX085YF672E5G | 10CL120YF780I7G |
|---|---|---|---|
| Package | 672-BGA (FBGA, F672) | 672-BGA (FBGA, F672) - same | 780-BGA (FBGA, F780) - different footprint |
| Brand | Intel | Intel | Intel |
| Logic Elements | 85,000 | 85,000 | 120,000 |
| Embedded Memory | 5,959,680 bits | 5,959,680 bits | 4,880,640 bits |
| DSP Blocks | 216 | 216 | 156 |
| Maximum User I/O | 192 | 192 | 277 |
| Process Node | 20 nm | 20 nm | 28 nm |
| Speed Grade | -6 | -5 | -7 |
| Operating Temperature | 0 C to +100 C | 0 C to +100 C | -40 C to +100 C (industrial) |
Key Differentiators
- Highest density Cyclone 10 GX in F672 package with hard PCIe Gen3 (vs 10CL120YF780I7G)
- Bitstream- and pin-compatible with 10CX085YF672E5G (vs 10CX085YF672E5G)
- Higher DSP count than Cyclone V same-tier (vs 10CL120YF780I7G)
Design Notes
Cyclone 10 GX devices require multi-rail sequencing per the pin connection guidelines. VCC (core, 0.9V) must ramp before VCCPT (1.0V PLL), and VCCIO must be present before VCCR/VCCT (transceiver) for proper configuration. Use a sequencer IC such as the LTC2974 or follow Intel's recommended RC network. Estimated: at 100% toggle on 85K LE plus 6 transceivers, ICC core draws roughly 1.5 A; verify with PowerPlay early in design.
The 672-BGA F672 package has a theta_JA of approximately 12 C/W with a standard 4-layer JEDEC test board and adequate via array under the BGA. Estimated: at 3 W total dissipation, junction temperature rise is 36 C above ambient; in an enclosed industrial enclosure at 70 C ambient, this leaves 19 C margin to the 100 C Tjmax. Always simulate with a real PCB stack-up, not JEDEC defaults.
Place decoupling capacitors within 1 mm of every VCC/VCCPT ball, using 0402-size 0.1 uF X7R plus bulk 22 uF per voltage rail. Maintain a continuous reference ground plane under the entire BGA and stitch the ground balls to it with 0.3 mm vias. Transceiver balls require 50 ohm controlled-impedance routing with length matching within 0.127 mm for 12.5 Gbps operation; refer to Intel's transceiver layout guidelines.
Do not assume Cyclone V bitstreams work in Cyclone 10 GX - they are NOT pin-compatible and configuration bitstream formats differ. Re-generate pin assignments in Quartus Prime and recompile. Another common pitfall is omitting the CFGBVS pin strap (high for 3.3V config, low for 1.8V); wrong strap causes silent configuration failure with no easy debug log.
Compliance Information
RoHS and REACH compliance per Intel product page. Industrial temperature grade 0 C to +100 C. Not AEC-Q100 qualified - automotive use requires specific device qualification.
