10CX105YU484E5G - Cyclone 10 GX FPGA 104K LE 484-UBGA | Intel
MPN: 10CX105YU484E5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $380 | $380.00 |
| 10 | $358 | $3,580.00 |
| 100 | $318 | $31,800.00 |
| 250 | $295 | $73,750.00 |
| 500 | $275 | $137,500.00 |
Drop-in alternatives for 10CX105YU484E5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10CX105YU484E6G
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$65.8 / Unit
View Datasheet →10CX105YU484I5G
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View Datasheet →10CX105YU484I6G
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$372 / Unit
View Datasheet →10CX085YU484E5G
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$82.4 / Unit
View Datasheet →10CX085YU484E6G
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$282 / Unit
View Datasheet →10CX085YU484I5G
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$85 / Unit
View Datasheet →10CX105YU484E5G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 GX |
| Logic Elements / Cells | 104,000 |
| Number of LABs/CLBs | 38,000 |
| Total RAM Bits | 8,641,536 (8.2 Mbit) |
| Number of I/O | 188 |
| Package | 484-UBGA (U484, 19x19 mm) |
| Supply Voltage - Core | 0.9 V |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C to 100°C (TJ) |
| Product Status | Active |
| Process Technology | 20 nm |
| RoHS Status | Compliant |
10CX105YU484E5G Pin Configuration
| Pin A1 | VCC — Core supply (0.9 V) |
| Pin A22 | GND — Ground |
| Pin B12 | IO_3V0_188 — User I/O - bank 3V0 |
| Pin F14 | REFCLK — Transceiver reference clock input |
| Pin K1 | VCCR — Transceiver RX supply |
| Pin K22 | VCCT — Transceiver TX supply |
| Pin AB11 | nCONFIG — Configuration control (active low) |
| Pin AB22 | MSEL0 — Configuration mode select 0 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX105YU484E5G is suitable for 7 applications: Industrial Machine Vision and Video Processing, Broadcast and Professional Video Equipment, PCIe Gen2 Endpoint and Root-Port Designs, Low-Cost Radar and Lidar Preprocessing, Industrial IoT Gateways and Protocol Bridges, Test and Measurement Instrumentation Front-Ends, High-Speed Networking Line Cards and Packet Processors.
Industrial Machine Vision and Video Processing
The 10CX105YU484E5G's 104K logic elements plus integrated 6.144 Gbps transceivers and variable-precision DSP blocks make it well-suited for industrial machine vision pipelines. With 188 user I/O the device can interface directly to multiple MIPI CSI-2 or LVDS image sensors through FPGA PHY IP, while the hard floating-point DSP subsystem accelerates convolutional and pre-processing kernels without consuming fabric resources. At typical 0.9 V core operation, a Cyclone 10 GX board can run a 4-lane CSI-2 aggregator plus H.264 encoding at well under 5 W, making it practical for enclosed factory environments with limited cooling. Place input capacitors within 5 mm of each VCC pin pair to maintain transceiver jitter margin.
Recommended
Broadcast and Professional Video Equipment
Broadcast video routers and 4K UHD format converters benefit from the 10CX105YU484E5G's combination of 8.2 Mbit embedded RAM and 188 I/O. M20K blocks serve as line buffers for color-space conversion and frame-rate upconversion, while hard memory controllers feed external DDR3 memory at up to 933 Mbps. The U484 package provides ample I/O banks for SDI (SMPTE 2200), HDMI, and DisplayPort interfaces through soft PHY IP. Compared with discrete ASSP video processors, the FPGA approach lets manufacturers ship a single board design with multiple product variants differentiated only by the Quartus bitstream - significantly reducing inventory and SKU complexity. PCB stackup should target 100 ohm differential for SDI/HDMI lanes.
Recommended
PCIe Gen2 Endpoint and Root-Port Designs
The 10CX105YU484E5G integrates hard PCIe Gen2 IP cores with up to x4 lane support and integrated transceivers, eliminating the need for external bridge chips in many low-cost PCIe applications. The hard IP includes the transaction layer, data link layer, and PHY 3, freeing the 104K logic elements for application-layer DMA engines, NVMe controllers, or protocol analyzers. With 188 user I/O the device can drive a board's worth of peripheral buses alongside the PCIe link. The 484-UBGA package keeps the PCB footprint small enough for half-height, half-length cards while providing adequate power and ground balls for the 100 MHz reference clock. Expect ~3 W additional power when PCIe Gen2 x4 is fully utilized.
Recommended
Low-Cost Radar and Lidar Preprocessing
Automotive and industrial radar/lidar sensor front-ends use FPGAs to aggregate raw ADC samples and run CFAR detection, FFT preprocessing, and point-cloud clustering before forwarding to a host processor. The 10CX105YU484E5G's variable-precision DSP blocks deliver the multiply-accumulate throughput needed for FFT-based preprocessing, while the 6.144 Gbps transceivers carry the digitized RF data from ADCs. At 104K LEs, a Cyclone 10 GX 10CX105 can implement a 4-channel radar preprocessor with sufficient margin for the host-side protocol stack. Industrial-temp variants (10CX105YU484I5G) extend operation to -40C, suitable for outdoor sensor enclosures.
Recommended
Industrial IoT Gateways and Protocol Bridges
Industrial IoT gateways aggregate multiple fieldbus protocols (PROFINET, EtherCAT, Modbus TCP, EtherNet/IP) into a single uplink. The 10CX105YU484E5G's combination of transceivers, embedded memory, and 188 I/O allows a single chip to host multiple soft real-time Ethernet controllers with deterministic latency, while the 8.2 Mbit RAM provides frame buffers for QoS scheduling. The 484-UBGA package footprint fits in DIN-rail gateway form factors. Compared to running multiple protocol-specific ASSPs, the FPGA approach reduces BOM and enables field upgrades to new protocols via bitstream updates. Industrial-temp variants support -40C cabinet mounting.
Recommended
Test and Measurement Instrumentation Front-Ends
Bench-top oscilloscopes, logic analyzers, and protocol testers use FPGAs as the central data-acquisition and processing engine. The 10CX105YU484E5G's 188 user I/O can directly sample LVDS or parallel CMOS ADC data at hundreds of MSPS, while M20K blocks serve as deep acquisition memory. Hard transceivers can serialize acquired waveforms for streaming to a host over 10 Gbps Ethernet or USB 3.1. The 104K LE capacity allows integration of trigger logic, decoders (e.g. PCIe, I3C), and on-screen display generation within a single chip. Compared with multi-chip ASSP+FPGA designs, the single-chip approach simplifies board layout and reduces trigger latency.
Recommended
High-Speed Networking Line Cards and Packet Processors
Edge and access networking equipment such as 1G/10G Ethernet switches, industrial routers, and TSN bridges benefit from the 10CX105YU484E5G's integrated 6.144 Gbps transceivers and 188 I/O. Multiple soft 10G MAC IP cores can be instantiated alongside Ethernet PCS IP to build a small port-count aggregation switch or protocol converter. The 8.2 Mbit embedded RAM provides packet buffer space, while 104K LEs accommodate ACL matching, QoS scheduling, and OAM processing. Compared with hard-wired switching ASSPs, the FPGA approach supports incremental feature development and field upgrades. Industrial-temp variants support outdoor cabinet deployment.
Recommended
Recommended Products Summary
Engineering reference data for 10CX105YU484E5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX105YU484E6G | 10CX105YU484I5G | 10CX085YU484E5G | 10CX085YU484E6G | 10CX085YU484I5G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 484-UBGA (U484) | 484-UBGA (U484) - same | 484-UBGA (U484) - same | 484-UBGA (U484) - same | 484-UBGA (U484) - same | 484-UBGA (U484) - same |
| Logic Elements | 104,000 | 104,000 | 104,000 | 85,000 (-18%) | 85,000 (-18%) | 85,000 (-18%) |
| Embedded RAM (bits) | 8,641,536 | 8,641,536 | 8,641,536 | Lower (Cyclone 10 GX 85K variant) | Lower (Cyclone 10 GX 85K variant) | Lower (Cyclone 10 GX 85K variant) |
| User I/O | 188 | 188 | 188 | 188 | 188 | 188 |
| Speed Grade | E5 | E6 (faster) | E5 | E5 | E6 (faster) | E5 |
| Temperature Grade | Commercial 0C to 100C | Commercial | Industrial -40C to 100C | Commercial | Commercial | Industrial -40C to 100C |
| Core Voltage | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V |
Key Differentiators
- Higher logic density at the same U484 footprint (vs 10CX085YU484E5G)
- Industrial-temp variant available in identical footprint (vs 10CX105YU484E5G vs 10CX105YU484I5G)
- Faster speed-grade available without package change (vs 10CX105YU484E5G vs 10CX105YU484E6G)
Design Notes
Estimated: at typical Quartus Prime utilization around 70% LE, 50% M20K, 50% DSP, and 4 active transceiver channels, the 10CX105YU484E5G draws approximately 4-6 W from the 0.9 V core rail plus 1-2 W from VCCPT, VCCA_PLL, and VCCR/VCCT combined. Decouple each VCC pair with one 22 uF bulk + two 4.7 uF mid-frequency + one 0.1 uF high-frequency ceramic capacitor. Place bulk caps within 10 mm and 0.1 uF caps within 2 mm of the respective supply balls. Sequencing is critical: VCC must ramp before VCCPT, and both must be stable before VCCR/VCCT power up to prevent latch-up.
Estimated: with 6 W total dissipation in the 484-UBGA package (theta_JA approximately 15 C/W for a 4-layer JEDEC board), the junction-to-ambient rise is around 90 C, well above the 100 C junction limit when ambient is already 25 C. Place the FPGA in the center of the PCB with thermal via arrays under the central BGA ground balls to spread heat to inner copper planes. For enclosed chassis with limited airflow, consider a small clip-on heatsink or thermal pad to chassis wall. Industrial-temp variant (10CX105YU484I5G) may be required if ambient exceeds 70 C.
Use 1 oz copper on outer layers and 0.5 oz on inner layers for the 484-UBGA breakout. Microvia-in-pad is recommended for the inner rows of the BGA to escape the 0.8 mm pitch ball grid. Reference Intel Cyclone 10 GX hardware reference manual PCB guidelines - keep transceiver lanes matched within 0.13 mm differential pair length, route VCCR/VCCT as wide traces or planes, and isolate the REFCLK from switching signals by at least 4X the trace-to-trace spacing. Keep all BGA balls soldered; missing balls on UBGA packages cause intermittent contact failures that are extremely difficult to diagnose.
Transceiver channels need a 100 ohm differential impedance with intra-pair skew below 1 ps per cm of route length. Place AC-coupling capacitors within 25 mm of the FPGA transmitter balls with no more than 1 pF parasitic capacitance to ground. Use a low-jitter oscillator (below 1 ps RMS jitter) for the REFCLK input - XO vs MEMS oscillator choice depends on temperature stability requirements; MEMS oscillators offer better stability for industrial-temp deployments. Match all transceiver supply decoupling to within 5 mm of the VCCR/VCCT balls.
Do not leave MSEL pins floating - strap them to GND or VCC through 1 kohm resistors to select the desired configuration mode (typically AS or FPP for EPCQ flash). Do not use a JTAG header without ESD protection; the 484-UBGA is sensitive to ESD during board bring-up. Do not enable more transceiver channels than your PCB layout can route while maintaining 100 ohm impedance - over-subscribed transceiver routing is the most common cause of link training failures. Finally, do not power the device from a 0.9 V supply with poor transient response - the Cyclone 10 GX core can spike to 15 A in microseconds during logic activity.
Compliance Information
RoHS and REACH compliance per verified distributor listing. AEC-Q100 not applicable for FPGA in non-automotive primary mission - the part is not AEC-Q100 qualified per the Intel Cyclone 10 GX datasheet family note. Choose 10CX105YU484I5G for industrial-temp deployments.
