5M240ZT144I5N - MAX V CPLD, 240 LE, TQFP-144 | Intel
MPN: 5M240ZT144I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $21.24 | $21.24 |
| 10 | $19.5 | $195.00 |
| 100 | $17.2 | $1,720.00 |
| 500 | $15.4 | $7,700.00 |
| 1,000 | $13.8 | $13,800.00 |
Drop-in alternatives for 5M240ZT144I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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5M240ZT144C5N
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View Datasheet →5M240ZT144A5N
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View Datasheet →5M1270ZT144I5N
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View Datasheet →5M1270ZT144C5N
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View Datasheet →5M240ZT100I5N
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View Datasheet →5M240ZT144I5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device Logic Elements | 240 LE |
| Number of Logic Array Blocks | 12 LAB |
| Maximum User I/O Pins | 114 |
| User Flash Memory (UFM) | 8 Kbits |
| Internal Core Voltage | 1.8 V |
| I/O Bank Voltage | 1.2 V to 3.3 V (multi-voltage) |
| Speed Grade | I5 (industrial, -40 C to +100 C) |
| Package | TQFP-144 (T144) 22x22 mm |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 C to +100 C (industrial) |
| Configuration Memory | Non-volatile (flash) |
| Programming Interface | JTAG (IEEE 1149.1) |
| Standby Current (typical) | <1 mA |
| RoHS Status | Compliant |
5M240ZT144I5N Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | GND — Ground |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | I/O — User I/O pin (bank 1) |
| Pin 16 | I/O — User I/O pin (bank 1) |
| Pin 17 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 1) |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O pin (bank 1) |
| Pin 23 | I/O — User I/O pin (bank 1) |
| Pin 24 | I/O — User I/O pin (bank 1) |
| Pin 25 | I/O — User I/O pin (bank 1) |
| Pin 26 | I/O — User I/O pin (bank 1) |
| Pin 27 | I/O — User I/O pin (bank 1) |
| Pin 28 | VCCINT — Internal core supply (1.8 V) |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | I/O — User I/O pin (bank 2) |
| Pin 31 | I/O — User I/O pin (bank 2) |
| Pin 32 | I/O — User I/O pin (bank 2) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | I/O — User I/O pin (bank 2) |
| Pin 37 | I/O — User I/O pin (bank 2) |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 40 | I/O — User I/O pin (bank 2) |
| Pin 41 | I/O — User I/O pin (bank 2) |
| Pin 42 | I/O — User I/O pin (bank 2) |
| Pin 43 | I/O — User I/O pin (bank 2) |
| Pin 44 | GND — Ground |
| Pin 45 | I/O — User I/O pin (bank 2) |
| Pin 46 | I/O — User I/O pin (bank 2) |
| Pin 47 | I/O — User I/O pin (bank 2) |
| Pin 48 | I/O — User I/O pin (bank 2) |
| Pin 49 | I/O — User I/O pin (bank 2) |
| Pin 50 | I/O — User I/O pin (bank 2) |
| Pin 51 | I/O — User I/O pin (bank 2) |
| Pin 52 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 53 | I/O — User I/O pin (bank 2) |
| Pin 54 | I/O — User I/O pin (bank 2) |
| Pin 55 | I/O — User I/O pin (bank 2) |
| Pin 56 | I/O — User I/O pin (bank 2) |
| Pin 57 | GND — Ground |
| Pin 58 | I/O — User I/O pin (bank 3) |
| Pin 59 | I/O — User I/O pin (bank 3) |
| Pin 60 | I/O — User I/O pin (bank 3) |
| Pin 61 | I/O — User I/O pin (bank 3) |
| Pin 62 | VCCINT — Internal core supply (1.8 V) |
| Pin 63 | I/O — User I/O pin (bank 3) |
| Pin 64 | I/O — User I/O pin (bank 3) |
| Pin 65 | I/O — User I/O pin (bank 3) |
| Pin 66 | I/O — User I/O pin (bank 3) |
| Pin 67 | I/O — User I/O pin (bank 3) |
| Pin 68 | I/O — User I/O pin (bank 3) |
| Pin 69 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 70 | I/O — User I/O pin (bank 3) |
| Pin 71 | I/O — User I/O pin (bank 3) |
| Pin 72 | I/O — User I/O pin (bank 3) |
| Pin 73 | GND — Ground |
| Pin 74 | I/O — User I/O pin (bank 3) |
| Pin 75 | I/O — User I/O pin (bank 3) |
| Pin 76 | I/O — User I/O pin (bank 3) |
| Pin 77 | I/O — User I/O pin (bank 3) |
| Pin 78 | I/O — User I/O pin (bank 3) |
| Pin 79 | I/O — User I/O pin (bank 3) |
| Pin 80 | I/O — User I/O pin (bank 3) |
| Pin 81 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 82 | I/O — User I/O pin (bank 3) |
| Pin 83 | I/O — User I/O pin (bank 3) |
| Pin 84 | I/O — User I/O pin (bank 3) |
| Pin 85 | I/O — User I/O pin (bank 3) |
| Pin 86 | GND — Ground |
| Pin 87 | I/O — User I/O pin (bank 4) |
| Pin 88 | I/O — User I/O pin (bank 4) |
| Pin 89 | I/O — User I/O pin (bank 4) |
| Pin 90 | I/O — User I/O pin (bank 4) |
| Pin 91 | I/O — User I/O pin (bank 4) |
| Pin 92 | VCCINT — Internal core supply (1.8 V) |
| Pin 93 | I/O — User I/O pin (bank 4) |
| Pin 94 | I/O — User I/O pin (bank 4) |
| Pin 95 | I/O — User I/O pin (bank 4) |
| Pin 96 | I/O — User I/O pin (bank 4) |
| Pin 97 | I/O — User I/O pin (bank 4) |
| Pin 98 | I/O — User I/O pin (bank 4) |
| Pin 99 | GND — Ground |
| Pin 100 | I/O — User I/O pin (bank 4) |
| Pin 101 | I/O — User I/O pin (bank 4) |
| Pin 102 | I/O — User I/O pin (bank 4) |
| Pin 103 | I/O — User I/O pin (bank 4) |
| Pin 104 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 105 | I/O — User I/O pin (bank 4) |
| Pin 106 | I/O — User I/O pin (bank 4) |
| Pin 107 | I/O — User I/O pin (bank 4) |
| Pin 108 | I/O — User I/O pin (bank 4) |
| Pin 109 | GND — Ground |
| Pin 110 | I/O — User I/O pin (bank 4) |
| Pin 111 | I/O — User I/O pin (bank 4) |
| Pin 112 | TDI — JTAG Test Data In |
| Pin 113 | TMS — JTAG Test Mode Select |
| Pin 114 | TCK — JTAG Test Clock |
| Pin 115 | NC — Not connected (per datasheet) |
| Pin 116 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 117 | I/O — User I/O pin (bank 4) |
| Pin 118 | I/O — User I/O pin (bank 4) |
| Pin 119 | I/O — User I/O pin (bank 4) |
| Pin 120 | I/O — User I/O pin (bank 4) |
| Pin 121 | I/O — User I/O pin (bank 4) |
| Pin 122 | GND — Ground |
| Pin 123 | I/O — User I/O pin (bank 4) |
| Pin 124 | I/O — User I/O pin (bank 4) |
| Pin 125 | I/O — User I/O pin (bank 4) |
| Pin 126 | I/O — User I/O pin (bank 4) |
| Pin 127 | I/O — User I/O pin (bank 4) |
| Pin 128 | I/O — User I/O pin (bank 4) |
| Pin 129 | VCCINT — Internal core supply (1.8 V) |
| Pin 130 | I/O — User I/O pin (bank 4) |
| Pin 131 | I/O — User I/O pin (bank 4) |
| Pin 132 | I/O — User I/O pin (bank 4) |
| Pin 133 | I/O — User I/O pin (bank 4) |
| Pin 134 | GND — Ground |
| Pin 135 | TDO — JTAG Test Data Out |
| Pin 136 | nSTATUS — Configuration status (active-low) |
| Pin 137 | CONF_DONE — Configuration done (active-high) |
| Pin 138 | nCE — Chip enable (active-low) |
| Pin 139 | nCONFIG — Configuration control (active-low) |
| Pin 140 | I/O — User I/O pin (bank 1) |
| Pin 141 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 142 | I/O — User I/O pin (bank 1) |
| Pin 143 | I/O — User I/O pin (bank 1) |
| Pin 144 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M240ZT144I5N is suitable for 6 applications: I/O Expansion and Bus Bridging, Power Management and Sequencing Controller, LED Driver and Display Multiplexing, Configuration and Reset Control for FPGAs/ASICs, Industrial Control and Sensor Aggregation, Consumer Product Glue Logic.
I/O Expansion and Bus Bridging
The 5M240ZT144I5N's 240 Logic Elements and 114 user I/O pins make it ideal for I/O expansion and protocol bridging between incompatible voltage domains or bus standards in industrial controllers. With multi-voltage I/O support from 1.2 V to 3.3 V, it can directly interface to legacy 5 V-tolerant buses (via external resistors) and modern low-voltage processors simultaneously. Its instant-on non-volatile flash configuration eliminates boot delay, which is critical for systems that must respond to control signals within microseconds of power-up. Common use cases include SPI-to-I2C bridging, GPIO expansion, and address decoding between processors and peripherals. Recommended companion parts: MAX V JTAG programming cable, level shifters.
Recommended
Power Management and Sequencing Controller
The 5M240ZT144I5N is widely used as a multi-rail power-sequencing controller in FPGA-based boards, ATCA systems, and embedded compute modules. Its deterministic timing, JTAG programmability, and 8 Kbit User Flash Memory enable storage of sequencing profiles that adapt at runtime. With sub-1 mA standby current, it consumes negligible power when idle, and the industrial -40 C to +100 C temperature range handles harsh environments. Engineers use it to implement reset distribution, fault monitoring, and PG (power-good) signal aggregation. The instant-on behavior ensures controlled power-up of downstream regulators and ASICs the moment VCC ramps, eliminating race conditions.
Recommended
LED Driver and Display Multiplexing
With 114 user I/O pins, the 5M240ZT144I5N can drive large LED arrays, 7-segment displays, and dot-matrix panels without external driver ICs. Its CMOS I/O structure supports typical LED current sink requirements when paired with appropriate current-limiting resistors or constant-current drivers. The MAX V CPLD's instant-on behavior means displays light immediately at power-up without the configuration delay of an FPGA, which is ideal for always-on indicators and front-panel controls. The 8 Kbit UFM can store animation patterns, brightness profiles, or test sequences that the CPLD executes autonomously. Recommended for HMI front panels, status indicators, and decorative lighting controllers.
Recommended
Configuration and Reset Control for FPGAs/ASICs
The 5M240ZT144I5N frequently serves as a configuration watchdog for FPGAs and ASICs that require controlled initialization. It can hold a downstream device in reset until all prerequisite supplies are stable, then release the reset in a precise sequence, and monitor configuration DONE signals to gate system-level bring-up. Its flash-based non-volatile design ensures the configuration controller is ready before the FPGA even begins its boot sequence. The 8 Kbit UFM provides storage for revision IDs, serial numbers, and security keys used during FPGA bitstream authentication. This pattern is common in telecom line cards, industrial PCs, and avionics subsystems.
Recommended
Industrial Control and Sensor Aggregation
In industrial PLCs, motor controllers, and sensor hubs, the 5M240ZT144I5N aggregates inputs from many low-speed sensors, performs local debouncing and thresholding, and presents a clean parallel interface to a host processor. Its industrial -40 C to +100 C temperature rating handles factory floor conditions, and the deterministic timing makes it suitable for safety-related glue logic where unexpected latency would be unacceptable. The multi-voltage I/O support enables direct connection to both 3.3 V microcontrollers and 5 V sensor arrays. JTAG in-system programmability supports field updates without desoldering, which simplifies long-life industrial equipment maintenance.
Recommended
Consumer Product Glue Logic
In consumer electronics such as set-top boxes, gaming peripherals, and home appliances, the 5M240ZT144I5N replaces dozens of discrete logic chips with a single programmable device. Its instant-on behavior means peripherals respond immediately at power-on, and its sub-1 mA standby current is ideal for always-on appliances. Designers use it to implement remote-control decoders, button-matrix scanners, audio routing, and HDMI/DVI signal switching control. The non-volatile flash storage means the design is locked at manufacturing and there is no bitstream to load, reducing BOM cost and complexity. RoHS compliance supports sale into worldwide consumer markets.
Recommended
Recommended Products Summary
Engineering reference data for 5M240ZT144I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M240ZT144C5N | 5M240ZT144A5N | 5M1270ZT144I5N | 5M240ZT100I5N |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-144 (T144) | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-100 (T100) - different |
| Logic Elements | 240 LE | 240 LE | 240 LE | 1270 LE | 240 LE |
| Temperature Grade | Industrial (-40 C to +100 C) | Commercial (0 C to +85 C) | Automotive | Industrial (-40 C to +100 C) | Industrial (-40 C to +100 C) |
| Speed Grade | I5 | C5 | A5 | I5 | I5 |
| User I/O Pins | 114 | 114 | 114 | 114 | 79 |
| User Flash Memory | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Internal Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Unit Price (qty 1) | $21.24 | $4.41 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Largest user I/O count in MAX V family at this LE density (vs 5M240ZT100I5N)
- Industrial temperature range for harsh environments (vs 5M240ZT144C5N)
- Cost-down flexibility with same-footprint density migration (vs 5M1270ZT144I5N)
- Non-volatile instant-on behavior vs FPGA bitstream load (vs Cyclone V FPGA)
Design Notes
The 5M240ZT144I5N requires separate VCCINT (1.8 V core) and VCCIO1-VCCIO4 (1.2 V to 3.3 V per bank) supplies. Place a 0.1 uF ceramic decoupling capacitor within 3 mm of each VCCINT and VCCIO pin; add a bulk 10 uF tantalum or ceramic cap at each supply rail entry point. Power sequencing between VCCINT and VCCIO is not required, but ensure all supplies ramp monotonically within datasheet-specified rise times. Estimate: at typical 240 LE utilization (50%) the device draws 15-25 mA total quiescent current.
Use a 4-layer PCB with continuous ground plane under the TQFP-144 package to minimize ground bounce and provide thermal relief. JTAG pins (TCK, TMS, TDI, TDO) must be brought to a test header or tag-connect footprint for in-system programming access. Keep I/O traces short (under 50 mm) to minimize reflections at the 3.3 V LVCMOS edge rates, and route clock inputs on inner layers with adjacent ground shielding. Estimated: a 4-layer 1.6 mm FR4 stack-up yields approximately 35 C/W theta-JA for this package.
Do not leave JTAG pins floating - tie TMS and TDI to VCCIO via 10 kohm pull-ups and leave TCK pulled low through 10 kohm for stable boundary-scan behavior. Avoid using the nCE (chip enable) pin as a logic input without consulting Quartus Prime documentation, as some legacy designs confuse nCE with nCONFIG. Ensure the UFM block is not overwritten by logic during ISP programming unless intentional. When migrating from MAX II or MAX IIZ designs, re-validate timing constraints because MAX V has slightly different delay specifications.
Although the 5M240ZT144I5N dissipates less than 50 mW typical, at maximum utilization (90% LE, high toggle rate) power can approach 200 mW. With a 35 C/W theta-JA estimate on a 4-layer board, this yields about 7 C temperature rise above ambient - well within the 100 C junction limit. No heatsink is required for typical operation. Verify with a thermal probe in production builds where environmental conditions exceed 70 C ambient.
Compliance Information
RoHS and lead-free compliant per Intel/Altera product page. Industrial temperature grade (-40 C to +100 C). Not AEC-Q100 qualified - choose 5M240ZT144A5N or contact Intel for automotive-grade MAX V variants. Halogen-free status not explicitly stated in verified data.
