5M570ZE64I5N - 570 LE MAX V CPLD, 64-EQFP | Intel
MPN: 5M570ZE64I5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $10.45 | $10.45 |
| 10 | $9.85 | $98.50 |
| 100 | $8.92 | $892.00 |
| 500 | $8.05 | $4,025.00 |
| 1,000 | $7.2 | $7,200.00 |
Drop-in alternatives for 5M570ZE64I5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M570ZE64I5
β Drop-Inπ Reference alternative (not in catalog)
5M570ZE64C5N
β Drop-Inπ Reference alternative (not in catalog)
5M160ZE64I5N
β Drop-Inβ In Stock
$4.13 / Unit
View Datasheet β5M240ZM68I5N
β Drop-Inβ In Stock
$2.0009 / Unit
View Datasheet β5M1270ZT144C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$12.5 / Unit
View Datasheet β5M2210ZF256C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$5.49 / Unit
View Datasheet β5M570ZE64I5N Maximum Ratings & Electrical Characteristics
| Series | MAX V |
| Programmable Type | In System Programmable |
| Number of Logic Elements / Blocks | 570 |
| Number of Macrocells | 440 |
| Number of User I/O | 54 |
| Propagation Delay tpd(1) Max | 9 ns |
| Internal Supply Voltage VCCINT | 1.71 V to 1.89 V (1.8 V typical) |
| Operating Temperature Range | -40 C to +100 C (TJ) |
| Mounting Type | Surface Mount |
| Package / Case | 64-TQFP Exposed Pad (EQFP-64) |
| Supplier Device Package | 64-EQFP (7x7 mm) |
| Configuration Memory | Non-volatile Flash |
| Programmable I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| Programming Interface | JTAG (IEEE 1149.1) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
5M570ZE64I5N Pin Configuration
| Pin 1 | I/O β User I/O pin (Bank 1) |
| Pin 2 | I/O β User I/O pin (Bank 1) |
| Pin 3 | I/O β User I/O pin (Bank 1) |
| Pin 4 | I/O β User I/O pin (Bank 1) |
| Pin 5 | I/O β User I/O pin (Bank 1) |
| Pin 6 | I/O β User I/O pin (Bank 1) |
| Pin 7 | I/O β User I/O pin (Bank 1) |
| Pin 8 | I/O β User I/O pin (Bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin (Bank 1) |
| Pin 11 | I/O β User I/O pin (Bank 1) |
| Pin 12 | I/O β User I/O pin (Bank 1) |
| Pin 13 | I/O β User I/O pin (Bank 1) |
| Pin 14 | I/O β User I/O pin (Bank 1) |
| Pin 15 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 16 | I/O β User I/O pin (Bank 1) |
| Pin 17 | I/O β User I/O pin (Bank 1) |
| Pin 18 | I/O β User I/O pin (Bank 1) |
| Pin 19 | I/O β User I/O pin (Bank 1) |
| Pin 20 | I/O β User I/O pin (Bank 1) |
| Pin 21 | I/O β User I/O pin (Bank 1) |
| Pin 22 | I/O β User I/O pin (Bank 1) |
| Pin 23 | I/O β User I/O pin (Bank 1) |
| Pin 24 | I/O β User I/O pin (Bank 1) |
| Pin 25 | I/O β User I/O pin (Bank 1) |
| Pin 26 | I/O β User I/O pin (Bank 1) |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin (Bank 2) |
| Pin 29 | I/O β User I/O pin (Bank 2) |
| Pin 30 | I/O β User I/O pin (Bank 2) |
| Pin 31 | I/O β User I/O pin (Bank 2) |
| Pin 32 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 33 | I/O β User I/O pin (Bank 2) |
| Pin 34 | I/O β User I/O pin (Bank 2) |
| Pin 35 | I/O β User I/O pin (Bank 2) |
| Pin 36 | I/O β User I/O pin (Bank 2) |
| Pin 37 | I/O β User I/O pin (Bank 2) |
| Pin 38 | I/O β User I/O pin (Bank 2) |
| Pin 39 | I/O β User I/O pin (Bank 2) |
| Pin 40 | TDI β JTAG Test Data In |
| Pin 41 | TMS β JTAG Test Mode Select |
| Pin 42 | TCK β JTAG Test Clock |
| Pin 43 | GND β Ground |
| Pin 44 | TDO β JTAG Test Data Out |
| Pin 45 | nCONFIG β Configuration control (pull high for normal operation) |
| Pin 46 | nSTATUS β Configuration status (open-drain) |
| Pin 47 | CONF_DONE β Configuration done indicator (open-drain) |
| Pin 48 | I/O β User I/O pin (Bank 2) |
| Pin 49 | I/O β User I/O pin (Bank 2) |
| Pin 50 | I/O β User I/O pin (Bank 2) |
| Pin 51 | I/O β User I/O pin (Bank 2) |
| Pin 52 | I/O β User I/O pin (Bank 2) |
| Pin 53 | VCCINT β Core supply voltage (1.8 V) |
| Pin 54 | I/O β User I/O pin (Bank 2) |
| Pin 55 | I/O β User I/O pin (Bank 2) |
| Pin 56 | I/O β User I/O pin (Bank 2) |
| Pin 57 | I/O β User I/O pin (Bank 2) |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β User I/O pin (Bank 2) |
| Pin 60 | I/O β User I/O pin (Bank 2) |
| Pin 61 | I/O β User I/O pin (Bank 2) |
| Pin 62 | I/O β User I/O pin (Bank 2) |
| Pin 63 | I/O β User I/O pin (Bank 2) |
| Pin 64 | I/O β User I/O pin (Bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M570ZE64I5N is suitable for 6 applications: Industrial I/O Expansion and Voltage Translation, Bus Bridge / Glue Logic for Microcontroller Systems, Power-Sequencer / Supervisory State Machine, LED Display Driver and Multiplexer, Legacy Interface Adapter / Protocol Converter, Test & Measurement Front-End Logic.
Industrial I/O Expansion and Voltage Translation
The 5M570ZE64I5N's 54 user I/O across flexible MultiVoltage banks (1.5/1.8/2.5/3.3 V) make it ideal for expanding microcontroller GPIO counts and translating between mixed-voltage domains in industrial PLCs and motor-control boards. Its 9 ns pin-to-pin propagation delay is fast enough to bridge asynchronous 1 MHz SPI buses without timing closure issues, while the non-volatile flash configuration means the translation map is locked in at power-on with no boot time. The -40 C to +100 C industrial temperature range survives cabinet and outdoor factory environments.
Recommended
Bus Bridge / Glue Logic for Microcontroller Systems
As glue logic between an ARM microcontroller and legacy parallel peripherals (FPGA configuration buses, SRAM/Flash, LCD panels), the 5M570ZE64I5N's 440 macrocells can decode complex chip-select maps and implement bus-arbitration state machines. The in-system programmability via JTAG means engineers can iterate bus-protocol fixes without re-spinning the PCB, while 9 ns combinatorial latency is more than adequate for 50-100 MHz equivalent bus cycles. CPLDs are deterministic where FPGAs would add boot latency, so the MAX V part often replaces an FPGA entirely in cost-sensitive glue roles.
Recommended
Power-Sequencer / Supervisory State Machine
For server, telecom, and ATX-style power-supervisor designs, the 5M570ZE64I5N's deterministic 9 ns delay and instant-on flash memory make it ideal as the master power-sequencer that drives PG (power-good) signals and ENABLE pins across 8-12 rails. Each macrocell can host a rail's enable latch and timing logic, with 440 macrocells handling typical 8-rail sequences plus redundancy and fault-recovery state. The -40 to +100 C industrial temperature grade and exposed-pad 64-EQFP thermal performance are proven in continuous-operation telecom shelves.
Recommended
LED Display Driver and Multiplexer
The 5M570ZE64I5N drives large LED walls, dot-matrix signs, and seven-segment multiplex displays by combining PWM generation, row/column scanning, and brightness-control state machines in a single low-power device. With 54 I/O and 9 ns delay, the CPLD can refresh up to 32-row multiplexed displays at >1 kHz per row with zero software overhead, freeing the host MCU for content. The 1.8 V core with 3.3 V-tolerant I/O also lets it interface directly to modern LED-driver ICs without level shifters.
Recommended
Legacy Interface Adapter / Protocol Converter
The 5M570ZE64I5N is widely used to bridge legacy interfaces (UART, SPI, I2C, parallel ports) to modern processors, where the CPLD handles protocol conversion, byte-level buffering, and voltage translation. The 570-LE capacity easily absorbs dual UART-to-SPI bridges plus GPIO expansion, while the deterministic 9 ns timing preserves serial-frame integrity at full baud rates up to several Mbaud. Non-volatile flash programming means the bridge boots in microseconds with no firmware updates required in the field.
Recommended
Test & Measurement Front-End Logic
For oscilloscope, logic-analyzer, and bench-instrument front-ends, the 5M570ZE64I5N's 9 ns delay supports high-speed channel switching, trigger-arm logic, and pattern generation at sub-100 MHz rates. The 54 I/O pins accommodate 16-channel multiplexer banks with margin for status LEDs and control lines. The 64-EQFP package with exposed pad simplifies thermal management in continuous-duty bench instruments that sit powered for hours, and the -40 to +100 C temperature range handles lab-to-warehouse thermal cycling.
Recommended
Recommended Products Summary
Engineering reference data for 5M570ZE64I5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M570ZE64I5 | 5M570ZE64C5N | 5M160ZE64I5N | 5M1270ZT144C5N | 5M2210ZF256C5N |
|---|---|---|---|---|---|---|
| Package | 64-EQFP (7x7 mm) | 64-EQFP (7x7 mm) - same | 64-EQFP (7x7 mm) - same | 64-EQFP (7x7 mm) - same | 144-TQFP (different) | 256-BGA (different) |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 570 | 570 | 570 | 160 (-72%) | 1270 (+123%) | 2210 (+288%) |
| Macrocells | 440 | 440 | 440 | 128 | 980 | 1700 |
| Max User I/O | 54 | 54 | 54 | 34 | [DATA_NEEDED] | [DATA_NEEDED] |
| Propagation Delay tpd(1) | 9 ns | 9 ns | Slower speed grade | 9 ns | 9 ns | [DATA_NEEDED] |
| Operating Temperature | -40 C to +100 C (Industrial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | -40 C to +100 C (Industrial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) |
| Configuration Memory | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash |
| Approx Unit Price @qty 1 (USD, as of 2026-09-06) | 10.45 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Mid-density MAX V CPLD with full industrial temperature range (vs 5M160ZE64I5N)
- 64-EQFP small footprint vs larger 100/144-TQFP MAX V options (vs 5M1270ZT144C5N)
- Non-volatile flash configuration vs SRAM-based FPGAs (vs Cyclone-series Intel FPGAs)
Design Notes
The 64-EQFP package exposes a thermal pad on the underside that MUST be soldered to a ground plane with at least 9 thermal vias in a 3x3 array (0.3 mm via drill, 0.6 mm pad) for proper heat dissipation and ground reference. Skipping the thermal pad connection will cause intermittent JTAG failures and 5-10 C higher junction temperature under continuous I/O switching. Place the 100 nF decoupling caps within 2 mm of every VCCINT and VCCIO pin, plus one 10 uF bulk cap near each voltage rail input.
Drive 64-EQFP outputs with a series 33 ohm damping resistor when traces exceed 25 mm or when the I/O toggles above 50 MHz, to suppress reflections on the JTAG and clock pins. Keep clock, JTAG, and global reset traces on the same layer as the device with a continuous ground return path. The MAX V 9 ns propagation delay assumes a 50 pF load; de-rate by 0.5 ns per additional 25 pF when driving long cables or large LED matrices.
Do not leave nCONFIG floating - tie it through a 10 kohm pull-up to VCCIO2. Without a proper pull-up, the CPLD may fail to enter user mode after power-up and the CONF_DONE pin will stay low. Also confirm VCCINT (1.8 V) is stable before VCCIO banks ramp; a 1 ms VCCINT-before-VCCIO sequence is recommended to prevent I/O latch-up. When programming via JTAG, ensure TCK is clean - a noisy JTAG clock is the #1 cause of verification failures on MAX V devices.
Compliance Information
RoHS-compliant per Intel MAX V family product page. AEC-Q100 not applicable (industrial-grade CPLD, not automotive-qualified). Halogen-free status not explicitly stated in distributor data; refer to Intel declaration for confirmation.
