ADS131E08SPAGR - 8-Ch 24-Bit 64-kSPS Delta-Sigma ADC | TI
MPN: ADS131E08SPAGR β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1 | $1.00 |
Drop-in alternatives for ADS131E08SPAGR β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
ADS131E08IPAGR
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ADS131E08SPAGR Maximum Ratings & Electrical Characteristics
| Resolution | 24 bit |
| Number of Channels | 8 (simultaneous sampling) |
| Sample Rate | up to 64 kSPS |
| ADC Architecture | Delta-Sigma |
| Input Type | Differential / Pseudo-differential |
| PGA | Built-in programmable gain amplifier |
| Internal Reference | Yes |
| Internal Oscillator | Yes |
| Interface | SPI |
| Analog Supply | 5 V |
| Digital Supply | 1.8 V |
| Power Consumption | 17.6 mW |
| Start-Up Time | Fast power-up (fast start-up) |
| Operating Temperature | -40C to +105C |
| Package | TQFP-64 (PAG) 10x10 mm |
| Mounting Type | Surface Mount |
| Packaging | Tape & Reel (R suffix) |
| Typical Application | Power monitoring and protection |
ADS131E08SPAGR Pin Configuration
| Pin 1 | MISO β SPI data output (DOUT) |
| Pin 2 | MOSI β SPI data input (DIN) |
| Pin 3 | SCLK β SPI serial clock |
| Pin 4 | CS β SPI chip select (active low) |
| Pin 5 | DRDY β Data ready indicator (active low) |
| Pin 6 | START β Conversion start control |
| Pin 7 | RESET β Device reset (active low) |
| Pin 8 | AVDD β Analog supply (5 V) |
| Pin 9 | AVSS β Analog ground |
| Pin 10 | DVDD β Digital supply (1.8 V) |
| Pin 11 | DGND β Digital ground |
| Pin 12 | INxP/INxN β Differential analog input pairs (channels 1-8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
ADS131E08SPAGR is suitable for 3 applications: Signal Conditioning, Data Acquisition, Audio Processing.
Signal Conditioning
Amplifying and filtering sensor signals using ADS131E08SPAGR.
Data Acquisition
Converting analog signals for digital processing with ADS131E08SPAGR.
Audio Processing
Audio signal amplification and processing with ADS131E08SPAGR.
No FAQ available for this product.
Engineering reference data for ADS131E08SPAGR β comparison, design guidance, and compliance information.
Selection Guide
Key Differentiators
- Eight channels in one package (vs ADS131E04SPAGR)
- Integrated AFE reduces BOM (vs AD7768BCPZ)
- Fast start-up for protection (vs ADS1258)
Design Notes
Provide separate analog (5 V AVDD) and digital (1.8 V DVDD) supply domains with independent decoupling: 1 uF ceramic directly at each supply pin plus 10 uF bulk per rail. Use a solid, unbroken ground plane under the TQFP-64 and keep the delta-sigma modulator clock region away from the SPI traces. Refer to TI ADS131E08 datasheet (SBAS) layout recommendations.
Route the SPI bus short and, in protection-relay environments, use digital isolators (e.g., TI ISO7721) between the ADC and the host MCU so switching noise from the digital side does not degrade the 24-bit noise floor. Keep anti-alias input RC filters close to INxP/INxN pins.
Do not leave the START pin floating - conversions only run when START is asserted. Respect the 1.8 V DVDD / 5 V AVDD supply ordering during power-up; violating supply sequencing can latch the device. Verify SPI timing (SCLK-to-DOUT delay) at full 64-kSPS data rate in your host driver.
Compliance Information
RoHS and lead-free status per TI product page. AEC-Q100 qualification not stated for this part.
