EP1810LC-35T - 900-Gate Classic EPLD, 35ns, 48 Macro Cells | Intel
MPN: EP1810LC-35T β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $176.66 | $176.66 |
| 10 | $158.5 | $1,585.00 |
| 100 | $142 | $14,200.00 |
| 500 | $128.75 | $64,375.00 |
| 1,000 | $115.2 | $115,200.00 |
Drop-in alternatives for EP1810LC-35T β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810LC-35
β Drop-Inβ In Stock
$49.2 / Unit
View Datasheet βEP1810LC-25T
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEP1810LC-30
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP1810LC-25
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEP1810LC-20T
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP1810LC-20
β Drop-Inβ In Stock
$7.85 / Unit
View Datasheet βEP1810LC-35T Maximum Ratings & Electrical Characteristics
| Device Family | EP1810 Classic EPLD |
| Product Type | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 900 |
| Macro Cells | 48 |
| Pin-to-Pin Delay (tpd) | 35 ns |
| Maximum Frequency (fmax) | 28.6 MHz |
| Supply Voltage (Vcc) | 5 V |
| Technology | CMOS |
| Logic Compatibility | 100% TTL emulation |
| Package | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Suffix | T = Tape and Reel |
| Operating Temperature | 0 C to +70 C (Commercial) |
| Mounting Type | Surface Mount (PLCC socket or direct solder) |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| RoHS Status | Non-compliant (legacy PLCC product) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL |
EP1810LC-35T Pin Configuration
| Pin 1 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 2 | I/O β General-purpose I/O pin |
| Pin 3 | I/O β General-purpose I/O pin |
| Pin 4 | I/O β General-purpose I/O pin |
| Pin 5 | I/O β General-purpose I/O pin |
| Pin 6 | I/O β General-purpose I/O pin |
| Pin 7 | I/O β General-purpose I/O pin |
| Pin 8 | I/O β General-purpose I/O pin |
| Pin 9 | I/O β General-purpose I/O pin |
| Pin 10 | I/O β General-purpose I/O pin |
| Pin 11 | GND β Ground (0 V) |
| Pin 12 | I/O β General-purpose I/O pin |
| Pin 13 | I/O β General-purpose I/O pin |
| Pin 14 | I/O β General-purpose I/O pin |
| Pin 15 | I/O β General-purpose I/O pin |
| Pin 16 | I/O β General-purpose I/O pin |
| Pin 17 | I/O β General-purpose I/O pin |
| Pin 18 | I/O β General-purpose I/O pin |
| Pin 19 | I/O β General-purpose I/O pin |
| Pin 20 | I/O β General-purpose I/O pin |
| Pin 21 | I/O β General-purpose I/O pin |
| Pin 22 | I/O β General-purpose I/O pin |
| Pin 23 | I/O β General-purpose I/O pin |
| Pin 24 | I/O β General-purpose I/O pin |
| Pin 25 | I/O β General-purpose I/O pin |
| Pin 26 | I/O β General-purpose I/O pin |
| Pin 27 | I/O β General-purpose I/O pin |
| Pin 28 | I/O β General-purpose I/O pin |
| Pin 29 | I/O β General-purpose I/O pin |
| Pin 30 | I/O β General-purpose I/O pin |
| Pin 31 | GND β Ground (0 V) |
| Pin 32 | I/O β General-purpose I/O pin |
| Pin 33 | I/O β General-purpose I/O pin |
| Pin 34 | I/O β General-purpose I/O pin |
| Pin 35 | I/O β General-purpose I/O pin |
| Pin 36 | I/O β General-purpose I/O pin |
| Pin 37 | I/O β General-purpose I/O pin |
| Pin 38 | I/O β General-purpose I/O pin |
| Pin 39 | I/O β General-purpose I/O pin |
| Pin 40 | I/O β General-purpose I/O pin |
| Pin 41 | I/O β General-purpose I/O pin |
| Pin 42 | I/O β General-purpose I/O pin |
| Pin 43 | I/O β General-purpose I/O pin |
| Pin 44 | I/O β General-purpose I/O pin |
| Pin 45 | I/O β General-purpose I/O pin |
| Pin 46 | I/O β General-purpose I/O pin |
| Pin 47 | I/O β General-purpose I/O pin |
| Pin 48 | I/O β General-purpose I/O pin |
| Pin 49 | I/O β General-purpose I/O pin |
| Pin 50 | I/O β General-purpose I/O pin |
| Pin 51 | GND β Ground (0 V) |
| Pin 52 | I/O β General-purpose I/O pin |
| Pin 53 | I/O β General-purpose I/O pin |
| Pin 54 | I/O β General-purpose I/O pin |
| Pin 55 | I/O β General-purpose I/O pin |
| Pin 56 | I/O β General-purpose I/O pin |
| Pin 57 | I/O β General-purpose I/O pin |
| Pin 58 | I/O β General-purpose I/O pin |
| Pin 59 | I/O β General-purpose I/O pin |
| Pin 60 | I/O β General-purpose I/O pin |
| Pin 61 | I/O β General-purpose I/O pin |
| Pin 62 | I/O β General-purpose I/O pin |
| Pin 63 | I/O β General-purpose I/O pin |
| Pin 64 | I/O β General-purpose I/O pin |
| Pin 65 | I/O β General-purpose I/O pin |
| Pin 66 | I/O β General-purpose I/O pin |
| Pin 67 | I/O β General-purpose I/O pin |
| Pin 68 | VCC β +5 V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-35T is suitable for 6 applications: 74LS TTL Logic Replacement, Microprocessor Address Decoding, Bus Interface Glue Logic, State Machine Implementation, Legacy 5 V System Sustainment, Multi-PAL/GAL Integration.
74LS TTL Logic Replacement
The EP1810LC-35T is purpose-built for replacing clusters of 74LS low-power Schottky TTL gates with a single programmable CMOS device, offering 100% TTL emulation at 5 V with substantially lower power consumption. With 900 usable gates and 48 macro cells, it can absorb the functionality of dozens of 74LS00, 74LS138, 74LS151, and 74LS374 ICs onto one die, simplifying board layout and BOM. The 35 ns pin-to-pin delay matches typical 74LS propagation delays (9-33 ns), preserving timing margins. Place the EP1810LC-35T in a 68-pin PLCC socket where the 74LS cluster originally lived, load the JEDEC file generated by MAX+PLUS II, and the device becomes a one-chip TTL replacement.
Recommended
Microprocessor Address Decoding
The EP1810LC-35T excels at microprocessor address decoding, generating chip-select signals for memory and peripheral maps from a single programmable device. Its 48 macro cells can implement complex address decode trees (e.g., 24-bit address decoding with multiple window comparisons) in one chip, replacing discrete 74LS138/139/85 decoder ICs. The 35 ns propagation delay fits comfortably within typical 8086/68000/80386 memory-access cycles of 200-500 ns, leaving ample setup time before chip-select assertion. Power the device from the 5 V rail, route address bus lines into inputs, configure macro cells as D flip-flops or combinatorial outputs, and program chip-select equations in MAX+PLUS II.
Recommended
Bus Interface Glue Logic
Glue logic between microprocessors, memory, and peripherals is a classic EP1810LC-35T use case, where the device arbitrates bus handshakes, generates wait-state timing, and bridges incompatible logic families. The 48 macro cells implement wait-state generators, bus buffers, parity generators, and interrupt controllers in a single device, replacing multiple 74LS245/373/245 buffers and 74LS123 one-shots. The 5 V TTL-compatible I/Os interface directly to 8086, 68000, Z80, and 8051 bus signals without level shifting. Place the EP1810LC-35T between the CPU and bus transceivers, route bus-control signals to inputs, and configure outputs to drive the bus-control logic.
Recommended
State Machine Implementation
The EP1810LC-35T is well-suited for state-machine controllers in industrial automation and instrumentation, where its 48 macro cells can implement 16-32 state FSMs with complex output decoding. Each macro cell functions as a D flip-flop with separate clock, preset, and clear controls, providing optimal state-register building blocks; the AND/OR array generates next-state and output logic. The 28.6 MHz toggle frequency supports state-transition rates well beyond mechanical-relay or operator-interface response times. Program state equations in MAX+PLUS II using AHDL or schematic entry, generate the JEDEC file, and burn it via a programming adapter into the device's UV-erasable CMOS array.
Recommended
Legacy 5 V System Sustainment
Sustaining legacy 5 V industrial, military, and aerospace systems whose original 74LS or PAL-based logic is now obsolete is a primary EP1810LC-35T application. The 68-pin PLCC package and 5 V tolerance match the original design's footprint and power rail exactly, allowing drop-in replacement of failed original Altera parts without PCB rework. Rochester Electronics and aftermarket distributors maintain limited stock of authentic Altera-die EP1810LC-35T devices for these sustainment programs. Use the part as a form-fit-function replacement, reuse the original JEDEC programming file, and avoid the extensive requalification that a different-package replacement would require.
Recommended
Multi-PAL/GAL Integration
The EP1810LC-35T integrates multiple PAL (Programmable Array Logic) and GAL (Generic Array Logic) devices onto a single chip, reducing board area, power, and BOM count in designs that originally used several 16V8, 20V8, or 22V10 PLDs. With 48 macro cells, the device can absorb the functionality of 4-6 standard 22V10 PALs, each consuming roughly 180 mA at 5 V, into one device consuming a fraction of the total power. Consolidate the PAL equations into a single MAX+PLUS II design, partition the I/O assignments, and program the resulting JEDEC file; the EP1810LC-35T replaces the entire PAL cluster with one socket.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-35T β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-35 | EP1810LC-25T | EP1810LC-30 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 68-pin PLCC (Tape & Reel) | 68-pin PLCC (Tube) - same | 68-pin PLCC (Tape & Reel) - same | 68-pin PLCC (Tube) - same |
| Pin-to-Pin Delay (tpd) | 35 ns | 35 ns | 25 ns | 30 ns |
| Maximum Toggle Frequency | 28.6 MHz | 28.6 MHz | 40 MHz (estimated, [DATA_NEEDED]) | 33.3 MHz (estimated, [DATA_NEEDED]) |
| Usable Gates | 900 | 900 | 900 | 900 |
| Macro Cells | 48 | 48 | 48 | 48 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
| Lifecycle Status | Obsolete (aftermarket only) | Obsolete (aftermarket only) | Obsolete (aftermarket only) | Obsolete (aftermarket only) |
| Programming Tool | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) |
Key Differentiators
- Tape-and-reel packaging for automated SMT assembly (vs EP1810LC-35 (tube))
- 35 ns speed grade is the slowest, lowest-cost option in the EP1810 family (vs EP1810LC-25T (25 ns))
- Authentic Altera/Intel silicon with documented heritage (vs Third-party remarked/recycled parts on open market)
Design Notes
The EP1810LC-35T cannot be programmed using modern Intel Quartus Prime software - it requires the legacy Altera MAX+PLUS II development environment (version 10.x or earlier) which is no longer officially distributed. To obtain MAX+PLUS II for legacy Classic EPLD support, search archived Altera FTP mirrors or contact Altera/Intel legacy support. A compatible programming adapter (e.g., Altera PL-ASAP or Logic Programmer) is also required to write the JEDEC file to the device. Programming file format is standard JEDEC (.jed), not the modern .pof format used by MAX II/MAX V devices.
The 68-pin PLCC package uses J-leads on a 1.27 mm pitch (50 mil) with a JEDEC MS-018 outline; provide either a PLCC socket (e.g., 3M 68-pin PLCC socket) for easy replacement or direct-solder the device to the board. For socket-mount designs, ensure socket standoff is 4.5 mm minimum above the PCB to allow chip-extractor clearance. Decouple VCC (pin 68) with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin, plus a 10 uF tantalum bulk capacitor on the same 5 V rail. Ground pins 11, 31, and 51 must all be connected to a low-impedance ground plane.
The EP1810LC-35T is NOT RoHS compliant due to the lead-based PLCC packaging and tin-lead solder plating; do not use this part in any design that must meet RoHS, REACH, or other lead-free directives. The plastic LC suffix indicates one-time-programmable (OTP) UV-opaque packaging, so design verification must be done with a windowed ceramic version (e.g., EP1810LC-35, EP1810GM883B) or in MAX+PLUS II simulation before committing the JEDEC file to production parts. Also note that EP1810 family speed-grade ordering (20 = fastest, 35 = slowest) is inverse to typical logic-part numbering - engineers familiar with 74LS naming may mis-order.
Compliance Information
EP1810 Classic EPLD family uses lead-bearing PLCC packaging and is not RoHS compliant. Reach and conflict-mineral status not stated in verified distributor data; classified as unknown. AEC-Q100 not applicable - this is a commercial-grade legacy programmable logic device with operating temperature 0 C to +70 C.
