EPC1C20 - Altera Enhanced Configuration Device 20-Pin PLCC | Intel
MPN: EPC1C20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.4 | $4,700.00 |
| 1,000 | $8.2 | $8,200.00 |
EPC1C20 Overview
An Enhanced Configuration Device is a type of serial configuration PROM that stores the bit-stream image for an Altera programmable logic device. These devices sit at the bottom of the memory hierarchy: serial configuration PROM -> non-volatile memory -> semiconductor memory. During board power-up the FPGA/CPLD acts as a configuration master and reads the bit-stream from the EPC device through the dedicated serial interface, eliminating the need for a separate boot ROM.
Key features include a single +5 V supply operation (with 3.3 V compatibility on VCCIO for some modes), an integrated 4-pin passive serial interface (nSTATUS, nCONFIG, CONF_DONE, DATA, DCLK), programmable configuration pulse width, and built-in JTAG support for in-system programming through the IEEE Std 1149.1 boundary-scan interface. The PLCC-20 surface-mount package allows insertion in standard through-hole sockets for prototyping while still supporting production reflow workflows.
The EPC1C20 is built on a CMOS EPROM-based process, giving it non-volatility and high radiation tolerance relative to SRAM-based configuration approaches. Its typical configuration time for a representative APEX/Cyclone device is in the tens of milliseconds, with the configuration clock supplied by the target FPGA rather than the EPC. Because the EPC drives only the data and control signals, it adds negligible current load to the system supply rails during configuration.
Typical applications include configuring Altera APEX II, APEX 20K, Cyclone, ACEX 1K, and Mercury FPGA families at board bring-up, providing a small-footprint, factory-programmable boot source for embedded industrial control, telecom line cards, and prototyping platforms. Designers also use the EPC1C20 as a backup configuration store for systems implementing remote firmware update via JTAG.
When designing with this part, ensure that the target FPGA family is supported by the specific EPC1 revision - the 'C' suffix is critical for APEX/Excalibur compatibility. Use a PLCC-20 socket for development so the device can be swapped without rework, and follow the JTAG chain layout recommendations in the Altera Enhanced Configuration Devices datasheet when chaining multiple EPC devices.
Drop-in alternatives for EPC1C20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1C20 (same form factor and footprint) β differing in Manufacturer.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC1C8
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPC2C20
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPC1C20 Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Product Type | Enhanced Configuration (EPC) Device / Serial Configuration PROM |
| Supported Altera Families | APEX II, APEX 20K, Cyclone, ACEX 1K, Mercury, Excalibur |
| Configuration Interface | Altera Passive Serial (PS), 4-pin (nSTATUS, nCONFIG, CONF_DONE, DATA, DCLK) |
| Supply Voltage (VCCINT) | 5.0 V nominal |
| I/O Voltage (VCCIO) | 3.3 V or 5.0 V |
| Programming Interface | JTAG (IEEE Std 1149.1) in-system programming |
| Memory Cell Technology | CMOS EPROM (non-volatile, one-time or reprogrammable) |
| Package | 20-pin PLCC (J-lead) |
| Mounting Type | Surface Mount (PLCC socket compatible for through-hole prototyping) |
| RoHS Status | unknown |
| Lead-Free / Halogen-Free | unknown |
| Lifecycle Status | Obsolete (NRND by Altera; supported stock only) |
| Configuration Clock Source | Target FPGA supplies DCLK (EPC is slave) |
| In-System Programmability | Yes (via JTAG) |
EPC1C20 Pin Configuration
| Pin 1 | nSTATUS β Open-drain status flag to FPGA (pulled low during configuration error) |
| Pin 2 | VCC β +5 V core supply |
| Pin 3 | GND β Ground |
| Pin 4 | DATA β Serial data output to FPGA |
| Pin 5 | DCLK β Configuration clock input from FPGA |
| Pin 6 | GND β Ground |
| Pin 7 | VCCIO β I/O supply (3.3 V or 5 V) |
| Pin 8 | nCONFIG β Configuration start control from FPGA / external reset |
| Pin 9 | CONF_DONE β Configuration complete flag (open-drain) |
| Pin 10 | NC β Not connected (per datasheet) |
| Pin 11 | TCK β JTAG test clock |
| Pin 12 | TMS β JTAG test mode select |
| Pin 13 | TDI β JTAG test data in |
| Pin 14 | TDO β JTAG test data out |
| Pin 15 | NC β Not connected (per datasheet) |
| Pin 16 | OE β Output enable (active low) - unused in PS mode, tie per datasheet |
| Pin 17 | nCE β Chip enable (active low) - tie low for always-selected |
| Pin 18 | VCC β +5 V core supply |
| Pin 19 | GND β Ground |
| Pin 20 | VCCIO β I/O supply (3.3 V or 5 V) |
Typical Applications
EPC1C20 is suitable for 6 applications: APEX 20K / Cyclone FPGA Boot Configuration, ACEX 1K Industrial Control Board Boot Source, Mercury / APEX II Telecom Line Card Configuration, Excalibur SoC Platform Configuration, JTAG-Programmable Factory Test Fixture, Legacy Avionics and Defense Configuration Memory.
APEX 20K / Cyclone FPGA Boot Configuration
The EPC1C20 stores the bit-stream image that loads into an Altera APEX 20K, ACEX 1K, or first-generation Cyclone FPGA at power-on. Its Passive Serial interface (DATA, DCLK, nCONFIG, nSTATUS) is slave-mode, so the target FPGA generates DCLK and reads configuration bits serially until CONF_DONE asserts. With 5 V VCCINT and 3.3 V / 5 V VCCIO flexibility, the EPC1C20 can be paired directly with APEX 20K and Cyclone devices that run on 5 V rails, eliminating the need for a parallel boot ROM.
Recommended
ACEX 1K Industrial Control Board Boot Source
For industrial control boards based on Altera ACEX 1K FPGAs, the EPC1C20 provides a single-chip non-volatile configuration memory that survives factory power cycles and field reset events. Its CMOS EPROM storage is more radiation-tolerant than SRAM FPGAs and is well-suited to factory-floor environments with -40 C to +85 C ambient temperature. Designers use the EPC1C20 to keep configuration cycles deterministic in motor-control and PLC applications where the FPGA must come up in a known state within tens of milliseconds of rail-valid assertion.
Recommended
Mercury / APEX II Telecom Line Card Configuration
Telecom line cards built on Altera Mercury or APEX II FPGAs used the EPC1C20 family to boot at 5 V and provide deterministic power-on behavior for hot-swap and OIR (online insertion and removal) scenarios. The EPC1C20's PS interface allows the line card FPGA to reconfigure itself from the EPC after a hot-extract event. JTAG access to the EPC1C20 enables remote firmware update over backplane test access ports, simplifying field upgrades in central-office equipment.
Recommended
Excalibur SoC Platform Configuration
Altera Excalibur SoC platforms (FPGA + embedded ARM core) use the EPC1C20 family to load the FPGA fabric bit-stream while the embedded processor boots from a separate flash. This split boot arrangement lets designers update the FPGA portion independently of the firmware, accelerating development of Excalibur-based prototypes. The 20-pin PLCC J-lead package is convenient for prototype sockets and is small enough to fit on compact Excalibur development boards.
Recommended
JTAG-Programmable Factory Test Fixture
Production test fixtures that configure multiple Altera FPGAs on a UUT (unit under test) use the EPC1C20 as the in-system programmable image source during board test. The EPC1C20's JTAG (IEEE 1149.1) interface lets the fixture's test controller re-image the EPC between test cycles without removing the part. This pattern is common in high-volume contract manufacturing where multiple SKUs share one test program and re-flash the EPC at test time.
Recommended
Legacy Avionics and Defense Configuration Memory
Long-lifecycle avionics and defense systems based on Altera APEX and ACEX FPGAs still deploy the EPC1C20 because it is non-volatile and EPROM-based (radiation-tolerant relative to SRAM). Obsolete-stock EPC1C20 is often procured through vetted distributors for repair and overhaul of fielded systems where the FPGA configuration cannot be changed without re-certification. The PLCC-20 socketed mounting eases field replacement when board-level repair is required.
Recommended
Recommended Products Summary
Engineering reference data for EPC1C20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1C8 | EPC2C20 |
|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-20 | PLCC-20 (same) | PLCC-20 (same) |
| Configuration Interface | Altera Passive Serial (PS) | Altera Passive Serial (PS) | Altera Passive Serial (PS) + multi-byte |
| Memory Density | C20 (mid) | C8 (low) | C20 (mid, larger EPROM cell) |
| Supported FPGA Families | APEX 20K, ACEX 1K, Cyclone, Mercury, Excalibur | Same families (smaller designs only) | APEX II / Mercury / APEX 20K / Cyclone (extended) |
| Multi-Byte Programming | No | No | Yes |
| JTAG In-System Programming | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| VCCINT Supply Voltage | 5.0 V | 5.0 V | 5.0 V |
| Lifecycle Status | Obsolete / NRND | Obsolete / NRND | Obsolete / NRND |
Key Differentiators
- Mid-density variant in the EPC1 family (vs EPC1C8)
- Lower cost and wider availability than EPC2C20 (vs EPC2C20)
- Single-footprint Altera / Intel configuration PROM family (vs Cross-brand Xilinx XCFxxS PROMs)
Design Notes
Place the EPC1C20 within 1-2 inches of the target FPGA's PS interface pins to minimize stub length and reflections on DATA and DCLK. Provide a 0.1 uF ceramic decoupling cap between VCC (pin 2 / 18) and ground, plus a 10 uF bulk cap near VCCIO. If the EPC1C20 is socketed for development, leave room for a PLCC-20 through-hole socket so the part can be swapped without reflow rework.
Do not use EPC1C20 with Cyclone IV, Cyclone V, Cyclone 10, or any Stratix family - those devices require EPCS/EPCQ Active Serial (AS) memories, not Passive Serial EPC1/EPC2 devices. nCONFIG and nSTATUS are open-drain on the EPC1C20 - both require a 1 kohm to 10 kohm pull-up resistor to VCCIO on the board; missing pull-ups cause the FPGA to never exit POR. CONF_DONE is also open-drain and must have a pull-up.
DCLK can run up to tens of MHz per the Altera datasheet PS timing specifications; route DCLK and DATA as a matched-length pair (within 200 mil) and keep them away from switching power or clock traces to avoid coupling. If the board supports both PS and JTAG configuration, place a 4-wire JTAG header (TCK/TMS/TDI/TDO) with a series 100 ohm resistor on each line near the EPC1C20 and follow the JTAG chain bypass recommendations from the datasheet.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status for EPC1C20 was not confirmed in the provided distributor data; the part predates the strict RoHS transition so it may be non-RoHS unless an explicit Intel/Altera RoHS-compliant part number suffix is documented. AEC-Q100 is not applicable for a configuration PROM.
