EPF10K20RI240-4 - FLEX 10K FPGA, 20K Gates, 240-Pin RQFP | Altera
MPN: EPF10K20RI240-4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $22.5 | $11,250.00 |
| 1,000 | $18.75 | $18,750.00 |
EPF10K20RI240-4 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnects, and I/O cells that the designer can re-program after manufacture to implement arbitrary digital logic. FPGAs sit hierarchically between CPLDs and ASICs/SoCs, and the FLEX 10K family was Altera's first family to embed dedicated array blocks (EABs) for on-chip synchronous RAM and ROM, advancing the architecture beyond simple glue-logic replacement.
Key features include in-system reconfigurability via SRAM configuration memory, support for 5 V PCI compliance, JTAG boundary-scan (IEEE 1149.1) for board test, built-in EAB blocks for 2 Kbit RAM/ROM each, and tri-state buffer on every I/O pin. The 240-pin RQFP footprint offers generous PCB escape routing and is widely supported by legacy design tools including Altera MAX+PLUS II and Quartus (legacy versions).
The FLEX 10K architecture combines a fine-grained logic fabric with coarse-grained embedded array blocks (EABs), giving designers both efficient random logic and high-density memory in a single die. Look-up tables (LUTs) implement the combinational logic, while the EABs provide synchronous memory with user-configurable width/depth, useful for FIFOs, ROM lookups, and DSP coefficient storage.
Typical applications include industrial control logic, telecommunications glue logic, glue logic for legacy 5 V microcontroller systems, PCI bus interface controllers, and prototyping of larger ASIC designs. The 5 V tolerance also makes it suitable for replacing older TTL/CMOS discrete logic in modernization programs.
When designing with this part, observe the 5 V supply rail and provide a clean decoupling network of 0.1 µF and 10 µF capacitors near every VCC/VCCIO pin pair. Configuration via the dedicated serial or parallel EPROM interface must be respected; modern MAX 10 or Cyclone devices are recommended for new designs, but the EPF10K20RI240-4 remains a drop-in solution for maintaining existing production.
This page synthesizes distributor pricing, same-package drop-in FLEX 10K alternatives, and practical design notes not aggregated on any single manufacturer or distributor page.
Drop-in alternatives for EPF10K20RI240-4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPF10K20RI240-4 (same form factor and footprint) — differing in Process Technology, RoHS Status, Family, Series, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF10K20RC240-4
✅ Drop-In✓ In Stock
$67.85 / Unit
View Datasheet →EPF10K20RI240-4N
✅ Drop-In📋 Reference alternative (not in catalog)
EPF10K20RC240-3
✅ Drop-In✓ In Stock
$21.2 / Unit
View Datasheet →EPF10K20RC240-3N
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →EPF10K50VRI240-4N
✅ Drop-In✓ In Stock
$49.95 / Unit
View Datasheet →EPF10K20RI240-4 Maximum Ratings & Electrical Characteristics
| Family | FLEX 10K |
| Series | EPF10K20 |
| Logic Elements / Cells | 1,152 |
| Total RAM Bits | 12,288 |
| Logic Array Blocks (LABs) | 144 |
| Number of Gates | 20,000 (typical) |
| User I/O Count | 189 |
| Maximum Operating Frequency | 125 MHz |
| Core Supply Voltage | 5 V |
| I/O Supply Voltage | 5 V |
| Process Technology | 0.42 µm CMOS (SRAM) |
| Package Type | 240-BFQFP / 240-RQFP with exposed pad |
| Operating Temperature Grade | Industrial |
| Configuration Memory | SRAM (volatile, external config device required) |
| Mounting Type | Surface Mount |
| RoHS Status | Non-compliant (legacy 5 V process) |
| Lead-Free | Contains lead (legacy) |
EPF10K20RI240-4 Pin Configuration
| Pin 1 | I/O — User I/O pin (function configured by Quartus/MAX+PLUS II bitstream) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | VCCINT — 5 V core supply |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | VCCIO — 5 V I/O supply |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | VCCINT — 5 V core supply |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | VCCIO — 5 V I/O supply |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | GND — Ground |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | VCCINT — 5 V core supply |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | GND — Ground |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | VCCIO — 5 V I/O supply |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | GND — Ground |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | VCCINT — 5 V core supply |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | GND — Ground |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | VCCIO — 5 V I/O supply |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | GND — Ground |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | VCCINT — 5 V core supply |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | GND — Ground |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | VCCIO — 5 V I/O supply |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | GND — Ground |
| Pin 101 | I/O — User I/O pin |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | I/O — User I/O pin |
| Pin 107 | VCCINT — 5 V core supply |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | GND — Ground |
| Pin 111 | I/O — User I/O pin |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | VCCIO — 5 V I/O supply |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | GND — Ground |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | VCCINT — 5 V core supply |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | GND — Ground |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | VCCIO — 5 V I/O supply |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | GND — Ground |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
| Pin 145 | I/O — User I/O pin |
| Pin 146 | I/O — User I/O pin |
| Pin 147 | VCCINT — 5 V core supply |
| Pin 148 | I/O — User I/O pin |
| Pin 149 | I/O — User I/O pin |
| Pin 150 | GND — Ground |
| Pin 151 | I/O — User I/O pin |
| Pin 152 | I/O — User I/O pin |
| Pin 153 | I/O — User I/O pin |
| Pin 154 | I/O — User I/O pin |
| Pin 155 | I/O — User I/O pin |
| Pin 156 | I/O — User I/O pin |
| Pin 157 | VCCIO — 5 V I/O supply |
| Pin 158 | I/O — User I/O pin |
| Pin 159 | I/O — User I/O pin |
| Pin 160 | GND — Ground |
| Pin 161 | I/O — User I/O pin |
| Pin 162 | I/O — User I/O pin |
| Pin 163 | I/O — User I/O pin |
| Pin 164 | I/O — User I/O pin |
| Pin 165 | I/O — User I/O pin |
| Pin 166 | I/O — User I/O pin |
| Pin 167 | VCCINT — 5 V core supply |
| Pin 168 | I/O — User I/O pin |
| Pin 169 | I/O — User I/O pin |
| Pin 170 | GND — Ground |
| Pin 171 | I/O — User I/O pin |
| Pin 172 | I/O — User I/O pin |
| Pin 173 | I/O — User I/O pin |
| Pin 174 | I/O — User I/O pin |
| Pin 175 | I/O — User I/O pin |
| Pin 176 | I/O — User I/O pin |
| Pin 177 | VCCIO — 5 V I/O supply |
| Pin 178 | I/O — User I/O pin |
| Pin 179 | I/O — User I/O pin |
| Pin 180 | GND — Ground |
| Pin 181 | I/O — User I/O pin |
| Pin 182 | I/O — User I/O pin |
| Pin 183 | I/O — User I/O pin |
| Pin 184 | I/O — User I/O pin |
| Pin 185 | I/O — User I/O pin |
| Pin 186 | I/O — User I/O pin |
| Pin 187 | I/O — User I/O pin |
| Pin 188 | I/O — User I/O pin |
| Pin 189 | I/O — User I/O pin |
| Pin 190 | I/O — User I/O pin |
| Pin 191 | I/O — User I/O pin |
| Pin 192 | TCK — JTAG Test Clock (IEEE 1149.1) |
| Pin 193 | TMS — JTAG Test Mode Select |
| Pin 194 | TDI — JTAG Test Data In |
| Pin 195 | TDO — JTAG Test Data Out |
| Pin 196 | nCONFIG — Configuration control (active-low) |
| Pin 197 | CONF_DONE — Configuration done status (open-drain) |
| Pin 198 | nSTATUS — Configuration status (active-low) |
| Pin 199 | DCLK — Configuration clock input |
| Pin 200 | DATA0 — Configuration data input |
| Pin 201 | I/O — User I/O pin |
| Pin 202 | I/O — User I/O pin |
| Pin 203 | I/O — User I/O pin |
| Pin 204 | I/O — User I/O pin |
| Pin 205 | I/O — User I/O pin |
| Pin 206 | I/O — User I/O pin |
| Pin 207 | I/O — User I/O pin |
| Pin 208 | I/O — User I/O pin |
| Pin 209 | I/O — User I/O pin |
| Pin 210 | I/O — User I/O pin |
| Pin 211 | I/O — User I/O pin |
| Pin 212 | I/O — User I/O pin |
| Pin 213 | I/O — User I/O pin |
| Pin 214 | I/O — User I/O pin |
| Pin 215 | I/O — User I/O pin |
| Pin 216 | I/O — User I/O pin |
| Pin 217 | I/O — User I/O pin |
| Pin 218 | I/O — User I/O pin |
| Pin 219 | I/O — User I/O pin |
| Pin 220 | I/O — User I/O pin |
| Pin 221 | I/O — User I/O pin |
| Pin 222 | I/O — User I/O pin |
| Pin 223 | I/O — User I/O pin |
| Pin 224 | I/O — User I/O pin |
| Pin 225 | I/O — User I/O pin |
| Pin 226 | I/O — User I/O pin |
| Pin 227 | I/O — User I/O pin |
| Pin 228 | I/O — User I/O pin |
| Pin 229 | I/O — User I/O pin |
| Pin 230 | I/O — User I/O pin |
| Pin 231 | I/O — User I/O pin |
| Pin 232 | I/O — User I/O pin |
| Pin 233 | I/O — User I/O pin |
| Pin 234 | I/O — User I/O pin |
| Pin 235 | I/O — User I/O pin |
| Pin 236 | I/O — User I/O pin |
| Pin 237 | I/O — User I/O pin |
| Pin 238 | I/O — User I/O pin |
| Pin 239 | I/O — User I/O pin |
| Pin 240 | I/O — User I/O pin |
Typical Applications
EPF10K20RI240-4 is suitable for 6 applications: Legacy Industrial Control Logic, Telecommunications Glue Logic, 5 V PCI Bus Interface Controllers, ASIC Prototyping and Emulation, Legacy Test and Measurement Equipment, Defense and Aerospace Avionics Backplanes.
Legacy Industrial Control Logic
The EPF10K20RI240-4's 1,152 logic cells, 189 user I/Os, and 5 V I/O tolerance make it a fit for industrial control systems originally designed in the late 1990s and early 2000s. Its 5 V PCI-compliant I/Os interface directly to legacy 5 V peripheral ASICs and bus transceivers without level shifters, and its 144 LABs provide enough logic density for motor control state machines, sensor fusion glue logic, and process I/O scanning. The 240-RQFP package supports wave-solder and selective-solder assembly still common in industrial production lines, and the industrial temperature grade (-40C to +85C) handles factory-floor thermal stress. Design teams maintaining 15- to 25-year-old controller PCBs use the EPF10K20RI240-4 as a long-term spare because migrating to a modern Cyclone 10 or MAX 10 part forces a complete PCB re-spin, re-certification, and re-validation.
Recommended
Telecommunications Glue Logic
Telecom equipment designed around the FLEX 10K era used the EPF10K20RI240-4 as flexible bus-interface glue logic between TDM backplanes, framer ASICs, and T1/E1 transceivers. The 189 user I/Os handle 8-/16-bit parallel bus widths plus JTAG and clock-tree fan-out, while the 12,288 bits of distributed RAM (via EABs) implement small FIFO buffers and elastic stores for rate adaptation. Its 5 V tolerance is critical because telecom backplanes of that era were predominantly 5 V TTL, and any non-5 V part would force costly level-translation. The EPF10K20RI240-4 also supports JTAG boundary-scan (IEEE 1149.1) for in-circuit test on high-density backplanes, a feature telecom OEMs required for their manufacturing test strategy. Obsolescence programs at tier-1 carriers are now the primary driver for sustaining stock of this part.
Recommended
5 V PCI Bus Interface Controllers
The EPF10K20RI240-4 natively supports 5 V PCI signaling at 33 MHz across all 189 user I/Os, making it a candidate for legacy PCI add-in cards and embedded PCI bridges where modern FPGAs (3.3 V only) cannot be used directly. Its 1,152 logic cells are sufficient to implement a PCI target or master state machine plus a custom application function (DSP, DMA, custom peripheral). The 12,288 RAM bits are used to back small descriptor tables and scatter-gather FIFOs, eliminating external SRAM on simple cards. Designers favor the 240-RQFP package because it offers 189 I/Os - enough for a 32-bit PCI bus plus local-bus expansion, address/data demultiplexing, and JTAG in a single device. This application is now restricted to long-life-cycle programs in medical imaging and defense, where re-certification costs make migration impractical.
Recommended
ASIC Prototyping and Emulation
In the late 1990s and early 2000s, the EPF10K20RI240-4 served as a high-density prototyping vehicle for ASIC designs that had not yet taped out. Its 1,152 logic cells emulated 20,000-30,000 gates of equivalent random logic with clock rates above 100 MHz, allowing verification of control logic, glue interfaces, and small DSP datapaths in real time. The 189 I/Os mapped almost directly to QFP-packaged ASICs, simplifying package-compatibility prototyping. The 12,288 bits of block RAM (via EABs) modelled register files and small FIFOs that would otherwise require behavioral simulation, dramatically reducing pre-silicon verification cycles. Modern ASIC prototyping uses multi-FPGA boards, but universities and small fabless teams still use individual EPF10K20RI240-4 devices as teaching platforms and pre-silicon test vehicles.
Recommended
Legacy Test and Measurement Equipment
Test-and-measurement instruments designed in the late 1990s - logic analyzers, protocol testers, arbitrary waveform generators - adopted the EPF10K20RI240-4 to integrate timing-control, pattern-generation, and trigger-sequencing logic into a single device. The 189 user I/Os directly drive front-panel connectors, instrument buses (GPIB/IEEE-488, RS-232, parallel), and high-speed probe interfaces. The 12 Kbits of internal RAM stores calibration tables and pattern sequences, eliminating external memory chips. The 125 MHz internal clock rate allows generation of high-precision digital stimuli for legacy parallel-bus standards (PCI, VME, VXI). Replacement is rare because test equipment has 15- to 30-year service lives, so calibration labs and ATE integrators maintain EPF10K20RI240-4 inventory to repair instruments still in active service.
Recommended
Defense and Aerospace Avionics Backplanes
Avionics subsystems designed in the late 1990s, particularly MIL-STD-1553 and ARINC 429 bridges, used the EPF10K20RI240-4 as a flexible bus-controller glue layer. Its 5 V tolerance matches legacy avionics power rails, and its 189 I/Os fan out across multiple redundant bus channels. The industrial temperature grade and ceramic-compatible 240-RQFP footprint support the conformal-coated PCB assemblies typical in airborne equipment. Although new avionics programs use modern rad-hard FPGAs, the EPF10K20RI240-4 remains in service life-extension programs for legacy military platforms (C-130, F-16, AH-64) where the cost of full avionics re-design exceeds the cost of maintaining obsolete FPGA stock. Approved-vendor lists continue to list the EPF10K20RI240-4 for depot-level repairs.
Recommended
Recommended Products Summary
Engineering reference data for EPF10K20RI240-4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF10K20RC240-4 | EPF10K20RI240-4N | EPF10K20RC240-3 | EPF10K20RC240-3N | EPF10K50VRI240-4N |
|---|---|---|---|---|---|---|
| Package | 240-RQFP / 240-BFQFP | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Cells | 1,152 | 1,152 | 1,152 | 1,152 | 1,152 | ~2,880 |
| User I/O Count | 189 | 189 | 189 | 189 | 189 | 189 |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial | Commercial | Industrial |
| Lead-Free / RoHS | SnPb (non-RoHS) | SnPb | Lead-free (RoHS) | SnPb | Lead-free (RoHS) | Lead-free (RoHS) |
| Total RAM Bits | 12,288 | 12,288 | 12,288 | 12,288 | 12,288 | 20,480 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Original 240-RQFP FLEX 10K industrial-temperature part with long field-proven history (vs EPF10K20RC240-4)
- Higher logic capacity in same footprint (upgrade path) (vs EPF10K10TC144-4)
- FLEX 10K legacy bitstream compatibility with modern toolchain support (vs EPF10K50VRI240-4N)
Design Notes
The EPF10K20RI240-4 requires a clean 5 V supply on both VCCINT (core) and VCCIO (I/O) rails. Place a 0.1 µF ceramic decoupling capacitor within 5 mm of every VCCINT/VCCIO pin pair, and add bulk 10 µF tantalum or aluminum-polymer capacitors near the package corners. Estimated: with all 189 I/Os switching at 33 MHz PCI rates, core current draw reaches 200-300 mA and I/O current can exceed 1 A transient; the 5 V regulator must supply at least 1.5 A continuous headroom. Add a ferrite bead in series with the I/O supply if analog/digital ground separation is required.
The 240-RQFP package has limited thermal dissipation due to its gull-wing lead frame. Estimated: at full 189-I/O switching load, total power dissipation is approximately 1-1.5 W, producing a junction temperature rise of 15-25 °C above ambient with the standard JEDEC still-air test board. For sealed industrial enclosures without forced airflow, derate the maximum ambient temperature by 10-15 °C. Exposed-pad variants improve thermal resistance by 30-40 % and should be selected for fanless designs.
Configuration memory is volatile SRAM - the EPF10K20RI240-4 loses its bitstream on every power-down. A configuration EPROM (EPC2, EPC4, EPC8, or EPC16) is mandatory. Do not leave nCONFIG floating during power-up; tie it through a 10 kΩ pull-up to VCC. CONF_DONE and nSTATUS are open-drain outputs and must also be pulled high externally. When migrating from a working EPF10K20RI240-4 design to a faster speed grade like the EPF10K20RC240-3, re-run static timing analysis in MAX+PLUS II - faster parts expose setup/hold violations that were timing-marginal at the slower speed.
Compliance Information
EPF10K20RI240-4 uses SnPb terminal finish and is not RoHS-compliant. The -4N variant is the RoHS-compliant equivalent. FPGAs are not subject to AEC-Q100 automotive qualification; military/aerospace programs rely on temperature-grade screening instead.
