EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
MPN: EPM240GM100C5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.85 | $7.85 |
| 10 | $7.2 | $72.00 |
| 100 | $6.1 | $610.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.75 | $4,750.00 |
EPM240GM100C5N Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PLDs and FPGAs in the programmable logic hierarchy: CPLD -> PLD -> programmable logic -> digital logic IC -> semiconductor. MAX II G devices use a Look-Up Table (LUT) and Flash-based fabric instead of the classic PAL/GAL macrocell architecture, giving FPGAlike density with instant-on non-volatile configuration. Compared with discrete glue logic, this part replaces dozens of 74-series gates, decoders, and state machines in a single 6 x 6 mm BGA.
Key features include 192 logic elements, 80 user I/Os, 4.7 ns tPD, in-system programmability via IEEE 1149.1 JTAG, multiVolt I/O supporting 1.5 V / 1.8 V / 2.5 V / 3.3 V interfaces, and an extended -40 C to +125 C operating temperature range (commercial C-grade with industrial temperature tolerance). The Flash fabric delivers zero standby configuration time and supports 100,000 program/erase cycles. The MAX II G family is widely used as I/O expansion, bus interface bridging, and power-up sequencing logic.
Typical applications include I/O expansion and level shifting in 3.3 V / 1.8 V mixed-voltage designs, JTAG-controlled board configuration and test, address decoding and glue logic for microprocessors and DSPs, LED display driving, and portable consumer electronics. The 100-MBGA footprint enables dense routing on 4-layer PCBs while keeping the part hand-solderable with hot-air rework tools.
When designing with this device, plan PCB escape routing for the 0.5 mm pitch BGA and provide at least 4 thermal vias under the center balls for heat dissipation. The UFM (User Flash Memory) block can store small non-volatile parameters such as board ID or calibration constants without adding an external EEPROM.
Drop-in alternatives for EPM240GM100C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM240GM100C5N (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, RoHS Status, Configuration Memory.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM240GF100C5N
✅ Drop-In✓ In Stock
$8.92 / Unit
View Datasheet →EPM240GF100I5N
✅ Drop-In✓ In Stock
$7.9 / Unit
View Datasheet →EPM240ZM100C5N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM240F100C5N
✅ Drop-In✓ In Stock
$5.2 / Unit
View Datasheet →5M240ZT100C5N
✅ Drop-In✓ In Stock
$4.9816 / Unit
View Datasheet →EPM240F100I5N
✅ Drop-In✓ In Stock
$5.2 / Unit
View Datasheet →EPM240GM100C5N Maximum Ratings & Electrical Characteristics
| Family | MAX II G |
| Logic Elements | 240 (192 macrocells) |
| User I/Os | 80 |
| Pin-to-Pin Delay (tPD) | 4.7 ns |
| Package | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| Ball Pitch | 0.5 mm |
| Supply Voltage - Core | 3.3 V |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP |
| Configuration Memory | Non-volatile Flash |
| Operating Temperature | -40 C to +125 C |
| Lead Free / RoHS | Yes / Compliant |
| MSL Level | 3 |
| Mounting Type | Surface Mount (BGA) |
| Process Technology | CMOS, Flash-based |
EPM240GM100C5N Pin Configuration
| Pin A1 | I/O — General-purpose user I/O (bank 1) |
| Pin A2 | I/O — General-purpose user I/O (bank 1) |
| Pin A3 | I/O — General-purpose user I/O (bank 1) |
| Pin A4 | I/O — General-purpose user I/O (bank 1) |
| Pin A5 | I/O — General-purpose user I/O (bank 1) |
| Pin A6 | I/O — General-purpose user I/O (bank 1) |
| Pin A7 | I/O — General-purpose user I/O (bank 1) |
| Pin A8 | I/O — General-purpose user I/O (bank 1) |
| Pin A9 | I/O — General-purpose user I/O (bank 1) |
| Pin A10 | I/O — General-purpose user I/O (bank 1) |
| Pin B1 | I/O — General-purpose user I/O (bank 1) |
| Pin B2 | I/O — General-purpose user I/O (bank 1) |
| Pin B3 | GND — Ground |
| Pin B4 | I/O — General-purpose user I/O (bank 1) |
| Pin B5 | I/O — General-purpose user I/O (bank 1) |
| Pin B6 | I/O — General-purpose user I/O (bank 1) |
| Pin B7 | I/O — General-purpose user I/O (bank 1) |
| Pin B8 | I/O — General-purpose user I/O (bank 1) |
| Pin B9 | I/O — General-purpose user I/O (bank 1) |
| Pin B10 | I/O — General-purpose user I/O (bank 1) |
| Pin C1 | I/O — General-purpose user I/O (bank 2) |
| Pin C2 | I/O — General-purpose user I/O (bank 2) |
| Pin C3 | I/O — General-purpose user I/O (bank 2) |
| Pin C4 | I/O — General-purpose user I/O (bank 2) |
| Pin C5 | VCCIO2 — I/O bank 2 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin C6 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin C7 | I/O — General-purpose user I/O (bank 1) |
| Pin C8 | I/O — General-purpose user I/O (bank 1) |
| Pin C9 | I/O — General-purpose user I/O (bank 1) |
| Pin C10 | I/O — General-purpose user I/O (bank 1) |
| Pin D1 | I/O — General-purpose user I/O (bank 2) |
| Pin D2 | I/O — General-purpose user I/O (bank 2) |
| Pin D3 | I/O — General-purpose user I/O (bank 2) |
| Pin D4 | I/O — General-purpose user I/O (bank 2) |
| Pin D5 | GND — Ground |
| Pin D6 | GND — Ground |
| Pin D7 | I/O — General-purpose user I/O (bank 1) |
| Pin D8 | I/O — General-purpose user I/O (bank 1) |
| Pin D9 | I/O — General-purpose user I/O (bank 1) |
| Pin D10 | I/O — General-purpose user I/O (bank 1) |
| Pin E1 | I/O — General-purpose user I/O (bank 2) |
| Pin E2 | I/O — General-purpose user I/O (bank 2) |
| Pin E3 | I/O — General-purpose user I/O (bank 2) |
| Pin E4 | I/O — General-purpose user I/O (bank 2) |
| Pin E5 | VCCINT — Core supply voltage (3.3 V) |
| Pin E6 | VCCINT — Core supply voltage (3.3 V) |
| Pin E7 | I/O — General-purpose user I/O (bank 1) |
| Pin E8 | I/O — General-purpose user I/O (bank 1) |
| Pin E9 | I/O — General-purpose user I/O (bank 1) |
| Pin E10 | I/O — General-purpose user I/O (bank 1) |
| Pin F1 | I/O — General-purpose user I/O (bank 2) |
| Pin F2 | I/O — General-purpose user I/O (bank 2) |
| Pin F3 | TDI — JTAG Test Data In |
| Pin F4 | TMS — JTAG Test Mode Select |
| Pin F5 | VCCINT — Core supply voltage (3.3 V) |
| Pin F6 | VCCINT — Core supply voltage (3.3 V) |
| Pin F7 | TCK — JTAG Test Clock |
| Pin F8 | TDO — JTAG Test Data Out |
| Pin F9 | I/O — General-purpose user I/O (bank 2) |
| Pin F10 | I/O — General-purpose user I/O (bank 2) |
| Pin G1 | I/O — General-purpose user I/O (bank 2) |
| Pin G2 | I/O — General-purpose user I/O (bank 2) |
| Pin G3 | I/O — General-purpose user I/O (bank 2) |
| Pin G4 | I/O — General-purpose user I/O (bank 2) |
| Pin G5 | GND — Ground |
| Pin G6 | GND — Ground |
| Pin G7 | I/O — General-purpose user I/O (bank 2) |
| Pin G8 | I/O — General-purpose user I/O (bank 2) |
| Pin G9 | I/O — General-purpose user I/O (bank 2) |
| Pin G10 | I/O — General-purpose user I/O (bank 2) |
| Pin H1 | I/O — General-purpose user I/O (bank 2) |
| Pin H2 | I/O — General-purpose user I/O (bank 2) |
| Pin H3 | I/O — General-purpose user I/O (bank 2) |
| Pin H4 | I/O — General-purpose user I/O (bank 2) |
| Pin H5 | VCCIO2 — I/O bank 2 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin H6 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin H7 | I/O — General-purpose user I/O (bank 1) |
| Pin H8 | I/O — General-purpose user I/O (bank 1) |
| Pin H9 | I/O — General-purpose user I/O (bank 1) |
| Pin H10 | I/O — General-purpose user I/O (bank 1) |
| Pin J1 | I/O — General-purpose user I/O (bank 2) |
| Pin J2 | I/O — General-purpose user I/O (bank 2) |
| Pin J3 | GND — Ground |
| Pin J4 | I/O — General-purpose user I/O (bank 2) |
| Pin J5 | I/O — General-purpose user I/O (bank 2) |
| Pin J6 | I/O — General-purpose user I/O (bank 1) |
| Pin J7 | I/O — General-purpose user I/O (bank 1) |
| Pin J8 | I/O — General-purpose user I/O (bank 1) |
| Pin J9 | I/O — General-purpose user I/O (bank 1) |
| Pin J10 | I/O — General-purpose user I/O (bank 1) |
Typical Applications
EPM240GM100C5N is suitable for 7 applications: I/O Expansion and Voltage Level Shifting, Address Decoding and Glue Logic for Microprocessors, JTAG-Controlled Board Configuration and Test, Power-Up Sequencing for Multi-Rail Systems, LED Display Driving and Visual Indicators, Portable and Battery-Powered Consumer Electronics, Industrial Control and Factory Automation.
I/O Expansion and Voltage Level Shifting
The EPM240GM100C5N's 80 user I/Os and multiVolt I/O support (1.5/1.8/2.5/3.3 V) make it ideal for I/O expansion and voltage translation in mixed-voltage designs. With 192 macrocells and 4.7 ns tPD, the device bridges 3.3 V microcontrollers to 1.8 V DDR memory or 5 V legacy peripherals without external level-shifters. The non-volatile Flash configuration eliminates boot delay, enabling instant-on behavior in real-time control systems. Placed between the MCU and peripheral bus with JTAG-controlled programming, it adds design flexibility while reducing BOM count versus discrete 74-series buffers.
Recommended
Address Decoding and Glue Logic for Microprocessors
With 192 macrocells and 4.7 ns pin-to-pin delay, the EPM240GM100C5N excels at address decoding, chip-select generation, and wait-state insertion for microprocessors, DSPs, and memory interfaces. The wide 80-I/O count supports 32-bit address/data buses plus control signals in a single device. The non-volatile Flash fabric ensures deterministic power-on behavior critical for processor boot sequences. Compared with discrete PAL/GAL devices, the MAX II G integrates UFM (User Flash Memory) for storing board ID and calibration constants, replacing an external EEPROM.
Recommended
JTAG-Controlled Board Configuration and Test
The EPM240GM100C5N's IEEE 1149.1 JTAG interface and in-system programmability make it ideal for board-level configuration, boundary-scan test, and field-upgradable logic. Engineers can re-route signals, fix design errors, or add features via JTAG without removing the part from the PCB - a major advantage over ASICs and discrete PALs. The 100,000 program/erase cycle endurance supports frequent firmware updates. Used as a JTAG-controlled switch matrix, it routes test vectors to multiple subsystems in production test fixtures.
Recommended
Power-Up Sequencing for Multi-Rail Systems
The EPM240GM100C5N is widely used to implement power-up and power-down sequencing in multi-rail systems such as FPGAs, ASICs, and complex SoCs. With 80 I/Os and deterministic 4.7 ns timing, the device generates precise enable signals for DC-DC converters, LDOs, and load switches in the correct order to prevent latch-up and in-rush current damage. The non-volatile configuration ensures the sequencing logic is active before any rail stabilizes, providing hardware-level safety independent of firmware boot state.
Recommended
LED Display Driving and Visual Indicators
The EPM240GM100C5N's 80 user I/Os and 4.7 ns tPD make it well suited for driving multiplexed LED matrices, 7-segment displays, and Charlieplexed indicator arrays. Each output can sink 25 mA per the MAX II G datasheet, enabling direct LED drive without external transistors. The Flash-based configuration stores custom blinking patterns and brightness PWM sequences that load instantly at power-up. Used in industrial control panels and consumer appliances, it replaces dozens of 74HC595 shift registers with a single BGA device.
Recommended
Portable and Battery-Powered Consumer Electronics
As a MAX II G 'zero-power' variant, the EPM240GM100C5N offers lower static current than the original MAX II, making it suitable for battery-powered and portable applications such as handheld instruments, wearables, and IoT edge devices. The 3.3 V core and 1.5 V multiVolt I/O directly interface modern low-power MCUs without level shifters. The non-volatile Flash fabric eliminates configuration current spikes at boot, extending battery life. Its 6 x 6 mm MBGA package fits space-constrained designs where every square millimeter matters.
Recommended
Industrial Control and Factory Automation
With its -40 C to +125 C operating range and RoHS-compliant construction, the EPM240GM100C5N is qualified for industrial control and factory automation equipment such as PLCs, motor controllers, and sensor interfaces. The non-volatile Flash configuration provides deterministic behavior critical for safety-related logic, and the 80 user I/Os handle multiple encoder, limit-switch, and relay-drive signals. JTAG ISP enables field updates to retrofit new features without board replacement, reducing total cost of ownership in long-lifecycle industrial installations.
Recommended
Recommended Products Summary
Engineering reference data for EPM240GM100C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240GF100C5N | EPM240ZM100C5N | 5M240ZT100C5N |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 100-MBGA (6 x 6 mm, 0.5 mm pitch) | 100-MBGA (6 x 6 mm) - same | 100-MBGA (6 x 6 mm) - same | 100-MBGA (6 x 6 mm) - same |
| Family | MAX II G | MAX II G | MAX II Z | MAX V |
| Logic Elements / Macrocells | 240 LE / 192 macrocells | 240 LE / 192 macrocells | 240 LE / 192 macrocells | 240 LE |
| User I/Os | 80 | 80 | 80 | 79 |
| tPD (Pin-to-Pin Delay) | 4.7 ns (C5) | 4.7 ns (C5) | 4.7 ns (C5) | 7.5 ns (C5) |
| Core Voltage | 3.3 V | 3.3 V | 1.8 V | 1.8 V |
| Static Current (typ) | Low (MAX II G zero-power) | Low (MAX II G) | Lower (MAX II Z) | Lowest (MAX V) |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C |
Key Differentiators
- Zero-power MAX II G variant with lower static current (vs EPM240F100C5N (MAX II non-G))
- Higher integration - 80 I/Os in compact 6 x 6 mm BGA (vs EPM240GT100C5N (TQFP package))
- Instant-on Flash configuration with no boot PROM (vs SRAM-based FPGAs (e.g., Cyclone series))
Design Notes
The 100-MBGA package has a 0.5 mm ball pitch on a 6 x 6 mm body. Use 0.4 mm via-in-pad (VIP) or microvia escape routing with at least 4 mil trace/space on a 4-layer PCB. Place a continuous GND plane on layer 2 directly under the BGA to provide a low-impedance return path and thermal spreading. Add 4 thermal vias (0.3 mm drill) under the center balls to keep junction temperature below 100 C at maximum toggle rate.
The EPM240GM100C5N requires two supply rails: VCCINT at 3.3 V (±5%) for the core, and VCCIO1/VCCIO2 at 1.5/1.8/2.5/3.3 V for the I/O banks. Decouple each VCCINT pin with a 0.1 uF X7R ceramic plus a 10 uF bulk capacitor within 50 mil. Place one 0.1 uF cap per VCCIO pin. Power-up sequencing is not required between VCCINT and VCCIO, but the JTAG controller must hold TMS high during VCC ramp to prevent inadvertent configuration.
Do not exceed the maximum I/O current of 25 mA per pin or 200 mA per bank. The MAX II G I/O is 5 V-tolerant only when VCCIO is 3.3 V and the input is below 4.0 V - do not apply 5 V signals when VCCIO is 1.8 V or damage will occur. Use Quartus II / Quartus Prime for programming; legacy MAX+PLUS II software does not support MAX II G silicon revisions.
For high-speed designs (>50 MHz), enable series 50 ohm termination on critical clock and JTAG signals by setting Quartus pin assignments to 'Weak Pull-Up' or 'Bus Hold' as appropriate. The MAX II G supports hot-socketing insertion without damage, but I/Os are tri-stated until configuration completes (~200 us). Route TDI/TMS/TCK away from switching I/O banks to avoid JTAG boundary-scan false triggers.
Compliance Information
RoHS compliant and lead-free per digchip datasheet record. Not AEC-Q100 qualified (consumer/industrial CPLD, not automotive-grade). MSL-3 moisture sensitivity per JEDEC J-STD-020.
