Altera

EPM7192SQC160-15 - MAX 7000S CPLD, 192 Macrocells, 15ns | Altera

MPN: EPM7192SQC160-15 ✗ End of Life

In Stock Ships in 1-3 business days

5.0 V Vdss PQFP-160 Package 76.9 MHz Speed EEPROM, non-volatile Memory

From $8.75 USD / Unit

MOQ: 1 |

Price updated: 2026-09-12

Volume Pricing

Qty	Unit Price	Extended
1	$16.85	$16.85
10	$14.95	$149.50
100	$12.4	$1,240.00
500	$10.2	$5,100.00
1,000	$8.75	$8,750.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EPM7192SQC160-15 Overview

The Altera EPM7192SQC160-15 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, based on Altera's second-generation MAX architecture. It provides 192 macrocells, 3,750 usable gates, 124 user I/Os, and a 15 ns pin-to-pin logic delay, all housed in a 160-pin PQFP package. The device operates at 5 V and supports 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the deterministic timing of PAL/GAL architectures with the density of multiple macrocell logic array blocks (LABs) interconnected via a programmable interconnect matrix (PIA). CPLDs sit between simple SPLDs/PLDs and FPGAs in the programmable logic hierarchy, offering fast, predictable input-to-output delays (suitable for glue logic and bus decoding) and instant-on configuration from on-chip EEPROM — without the external boot flash an FPGA usually requires.

Key features include 4 Logic Array Blocks (LABs) of 36 macrocells, programmable interconnect with 100% connectivity, programmable output slew rate, JTAG boundary-scan support, and macrocell registers with individual clear, preset, clock, and clock-enable controls. Operating frequency is specified at 76.9 MHz with a worst-case 15 ns tPD. The PQFP-160 package gives 124 usable I/O pins, suitable for high-fanout glue-logic designs.

The MAX 7000S architecture uses an EEPROM-based configuration cell array, so the device retains its logic pattern with no external boot memory and can be reprogrammed in-circuit up to 100 cycles. The 5.0-V ISP interface uses the standard 4-wire JTAG TAP, simplifying board-level bring-up. Each macrocell supports combinatorial or registered operation with separate sum-of-products terms for both output enable and registered feedback, giving flexible control over tri-state buses and registered outputs.

Typical applications include bus interface bridging, address decoding and glue logic for microprocessor systems, peripheral controller hubs, JTAG-controlled board-level configuration, and replacement of multiple discrete 74LS/74F/74HC TTL packages. It is also used in legacy industrial controllers and avionics subsystems where instant-on, non-volatile logic is mandatory.

When designing with this part, pay attention to the 5 V VCC requirement and observe the JTAG ISP programming voltage levels. Decoupling should follow the manufacturer guidance with 0.1 µF caps close to each VCC/GND pair. For new designs, consider MAX II or MAX V devices unless EEPROM-based instant-on is required.

This page consolidates distributor pricing, drop-in same-brand variants, and practical JTAG/ISP design notes not found in the original datasheet alone.

Drop-in alternatives for EPM7192SQC160-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPM7192SQC160-15 (same form factor and footprint) — differing in Operating Temperature, Package, Usable Gates, Supply Voltage (VCCINT), In-System Programmability.

EPM7160SQC160-10

Altera

Operating Temperature: 0 C to +70 C (commercial)

Package: PQFP-160 (SQC160)

Supply Voltage (VCCINT): 5.0 V