10AX115N2F40E2LG - Arria 10 GX FPGA, 1.15M LEs, FCBGA-1517 | Intel
MPN: 10AX115N2F40E2LG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2680 | $26,800.00 |
| 100 | $2450 | $245,000.00 |
| 500 | $2200 | $1,100,000.00 |
| 1,000 | $1980 | $1,980,000.00 |
Drop-in alternatives for 10AX115N2F40E2LG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AX115N2F40E1SG
β Drop-Inβ In Stock
$3325 / Unit
View Datasheet β10AX115N1F40E1SG
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$6995 / Unit
View Datasheet β10AX115N1F40E1LG
β Drop-Inπ Reference alternative (not in catalog)
10AX090N3F40E2LG
β Drop-Inβ In Stock
$2280 / Unit
View Datasheet β10AX090N2F40E2LG
β Drop-Inπ Reference alternative (not in catalog)
10AX090N2F40E1SG
β Drop-Inπ Reference alternative (not in catalog)
10AX115N2F40E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Adaptive Logic Modules (ALMs) | 42,720 |
| Embedded Memory | 68,857,856 bits (28.05 Mbits) |
| Maximum User I/O | 600 |
| High-Speed Transceivers | 24 (up to 17.4 Gbps) |
| Hardened PCIe | Gen3 x8, Gen2 x8 |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V (SmartVID) |
| Package | 1517-ball FC-BGA (F40) |
| Package Dimensions | 45 x 45 mm |
| Speed Grade | -2 |
| Operating Temperature | 0C to 100C (E2 commercial) |
| Memory Interfaces | DDR4 up to 2400 Mbps, DDR3, QDR IV, RLDRAM III |
| DSP Blocks | Hardened floating-point, up to 1.5 TFLOPs |
| Configuration Interface | JTAG, Active Serial, Fast Passive Parallel |
| RoHS Status | Compliant |
10AX115N2F40E2LG 45 x 45 mm Pin Configuration Guide
Complete pinout information for 10AX115N2F40E2LG (45 x 45 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115N2F40E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115N2F40E2LG is suitable for 6 applications: 4K Video Processing and Broadcast Equipment, Medical Imaging Systems (CT, MRI, Ultrasound), 100G Ethernet Line Cards and Network Equipment, Software Defined Radio and Wireless Baseband, Radar Signal Processing, High-Performance Computing Accelerators.
4K Video Processing and Broadcast Equipment
The 10AX115N2F40E2LG suits 4K video processing pipelines because it combines 1.15M logic elements for video processing cores with 24 transceivers operating at up to 17.4 Gbps for SDI, HDMI 2.0, and DisplayPort interfacing. The FPGA fabric can implement multiple simultaneous 4Kp60 streams, motion-adaptive deinterlacing, and high-dynamic-range tone mapping with hardware parallelism. Hardened Gen3 PCIe x8 accelerates host-side ingest of uncompressed video frames, while 28.05 Mbits of embedded memory buffers line and frame data. Power dissipation at 4K workload (estimated: ~25W core power at full DSP and transceiver utilization) is moderate, and the 45x45 mm FCBGA-1517 package provides adequate thermal mass. Placed on a 12-layer PCB with transceiver breakouts, the device drives broadcast routers, video wall controllers, and studio-grade encoder/decoders at lower cost than competing FPGAs in this density class.
Recommended
Medical Imaging Systems (CT, MRI, Ultrasound)
The 10AX115N2F40E2LG fits medical imaging back-end processing where high DSP performance and deterministic latency are mandatory. Its hardened floating-point DSP blocks deliver up to 1.5 TFLOPs of single-precision throughput, sufficient for back-projection reconstruction in CT scanners and beamforming in ultrasound systems. The 24 transceivers aggregate high-speed analog front-end ADC/DAC links at up to 17.4 Gbps, allowing direct interface to the latest JESD204B/C converters. Memory interfaces up to DDR4-2400 handle the high-bandwidth image data streams; the embedded M20K memory blocks provide low-latency line buffers for image rotation and filter kernels. With 1.15M logic elements, designers can implement image reconstruction, post-processing, and DICOM formatting in a single device. The commercial E2 temperature range (0C to 100C) accommodates controlled hospital equipment environments, and the Arria 10 medical designation confirms the part is qualified for medical applications per industry-standard documentation.
Recommended
100G Ethernet Line Cards and Network Equipment
The 10AX115N2F40E2LG targets 100G Ethernet line cards because its 24 transceivers at 17.4 Gbps can implement multiple 10G/25G ports or aggregate to 100G via gearbox logic in the FPGA fabric. With hardened Gen3 PCIe x8, the device interfaces directly to host CPUs or switch ASICs without soft logic overhead. The 28.05 Mbits of embedded memory provides packet buffer storage for cut-through switching, while the 600 user I/O pins support parallel backplane interfacing and external PHY connections. Designers can implement MAC, PCS, and forwarding logic with deep pipelining at 1.15M logic elements, fitting both 100G and 40G variants of line cards on the same PCB. The F40 FCBGA-1517 package supports the high pin count required for multi-port SERDES plus external memory, with the SmartVID core voltage of 0.9 V reducing per-port power. This makes the FPGA a strong fit for top-of-rack switches, OTN transport, and carrier-grade Ethernet platforms.
Recommended
Software Defined Radio and Wireless Baseband
The 10AX115N2F40E2LG supports software-defined radio (SDR) and wireless baseband processing, where 1.15M logic elements and hardened floating-point DSP deliver the throughput required for LTE, 5G NR, and custom waveform processing. The 24 transceivers at up to 17.4 Gbps accept high-sample-rate ADC/DAC data via JESD204B/C links, while 28.05 Mbits of embedded memory buffers sample streams between DSP blocks. Designers can implement FFT/iFFT, channel estimation, MIMO encoders/decoders, and beamforming weights in hardware with deterministic latency. The Arria 10 GX architecture offers better DSP-per-watt than older Stratix V parts for SDR workloads. With up to 600 user I/O pins, the device exposes antenna calibration, timing synchronization, and control interfaces. Operating temperature range of 0C to 100C handles controlled indoor base station environments, and the F40 FCBGA-1517 package accommodates the SERDES and memory bandwidth required by wideband RF digitizers.
Recommended
Radar Signal Processing
The 10AX115N2F40E2LG is suitable for radar signal processing in defense, weather, and automotive applications, where its hardened DSP blocks provide the floating-point throughput for pulse compression, MTI filtering, and Doppler processing. The 1.15M logic elements can implement phased-array beamforming for multiple simultaneous beams, while the 24 transceivers aggregate high-speed ADC data from antenna arrays. Embedded memory of 28.05 Mbits provides low-latency range-Doppler map storage between radar pulses. The F40 FCBGA-1517 package supports the pin density required for multi-channel SERDES and DDR4 buffer memory. With -2 speed grade, the device meets the timing margins needed for real-time radar processing at sub-millisecond refresh rates. Power dissipation scales with DSP utilization, and SmartVID reduces static power in idle intervals between scans. This makes the FPGA a good fit for ground-based, naval, and weather radar systems.
Recommended
High-Performance Computing Accelerators
The 10AX115N2F40E2LG accelerates HPC workloads as a co-processor in CPU-attached accelerator cards, exploiting 1.15M logic elements and hardened floating-point DSP blocks to deliver up to 1.5 TFLOPs of single-precision throughput per device. Hardened Gen3 PCIe x8 provides host link bandwidth of approximately 8 GB/s, while DDR4 memory interfaces at 2400 Mbps supply working data for matrix multiplication, FFT, and Monte Carlo simulation kernels. The 24 transceivers can drive multi-device expansion links via serial RapidIO or custom protocols for clustered HPC nodes. With embedded M20K memory blocks totaling 28.05 Mbits, designers implement low-latency systolic arrays without external SRAM. The F40 FCBGA-1517 package supports the SERDES, memory, and PCIe pin count required for accelerator cards, while SmartVID core voltage (0.9 V) reduces per-card power. This makes the part viable for financial simulation, computational genomics, and scientific computing deployments.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115N2F40E2LG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115N2F40E1SG | 10AX115N1F40E1SG | 10AX115N1F40E1LG | 10AX090N3F40E2LG | 10AX090N2F40E2LG | 10AX090N2F40E1SG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1517-ball FC-BGA (F40, 45x45 mm) | 1517-ball FC-BGA (F40, 45x45 mm) - same | 1517-ball FC-BGA (F40, 45x45 mm) - same | 1517-ball FC-BGA (F40, 45x45 mm) - same | 1517-ball FC-BGA (F40, 45x45 mm) - same | 1517-ball FC-BGA (F40, 45x45 mm) - same | 1517-ball FC-BGA (F40, 45x45 mm) - same |
| Logic Elements | 1,150,000 | 1,150,000 (same) | 1,150,000 (same) | 1,150,000 (same) | 900,000 (-22%) | 900,000 (-22%) | 900,000 (-22%) |
| Speed Grade | -2 | -1 (slower) | -1 (slower) | -1 (slower) | -2 (same) | -2 (same) | -1 (slower) |
| Embedded Memory | 28.05 Mbits (68,857,856 bits) | 28.05 Mbits (same) | 28.05 Mbits (same) | 28.05 Mbits (same) | Approx 22 Mbits (-22%) | Approx 22 Mbits (-22%) | Approx 22 Mbits (-22%) |
| High-Speed Transceivers | 24 (up to 17.4 Gbps) | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) |
| Maximum User I/O | 600 | 600 (same) | 600 (same) | 600 (same) | 600 (same) | 600 (same) | 600 (same) |
| Process Technology | 20 nm | 20 nm (same) | 20 nm (same) | 20 nm (same) | 20 nm (same) | 20 nm (same) | 20 nm (same) |
| Operating Temperature | 0C to 100C (E2 commercial) | 0C to 100C (E1 commercial) | 0C to 100C (E1 commercial) | 0C to 100C (E1 commercial) | 0C to 100C (E2 commercial) | 0C to 100C (E2 commercial) | 0C to 100C (E1 commercial) |
| Price (qty 1, approximate) | $2,850 | $2,750 (slightly lower) | $2,700 (slightly lower) | $2,700 (slightly lower) | $2,200 (-23%) | $2,150 (-25%) | $2,100 (-26%) |
Key Differentiators
- Higher logic density than 10AX090 family at same F40 footprint (vs 10AX090N3F40E2LG)
- Faster speed grade than -1 alternatives (vs 10AX115N2F40E1SG)
- Same F40 FCBGA-1517 footprint as 10AX090 family enables PCB reuse (vs 10AX090N2F40E2LG)
- Hardened PCIe Gen3 x8 IP saves logic resources (vs 10AS066K2F35E2SG)
Design Notes
Estimated: at full DSP and 24-transceiver utilization, the 10AX115N2F40E2LG dissipates approximately 25-30 W of core power. The F40 FCBGA-1517 package (45 x 45 mm) has a theta_JA in the range of 8-12 C/W with a properly designed heatsink and thermal interface material. Without a heatsink at full load, junction temperature could exceed 100 C. Designers must attach a heatsink with thermal resistance below 1 C/W and provide adequate airflow (recommended: 200 LFM minimum). The SmartVID feature adjusts core voltage dynamically to reduce static power in idle intervals, but active cooling is still required for sustained workloads.
The F40 FCBGA-1517 package requires a 12-layer PCB with high-speed stackup to route 24 transceivers at 17.4 Gbps and DDR4 memory interfaces at 2400 Mbps. Use low-loss laminate (e.g., Megtron 6 or equivalent) for transceiver channels, with reference plane continuity for all 100-ohm differential pairs. Matched-length routing within 5 mils for each SERDES lane and 25 mils for DDR4 byte lanes. AC coupling capacitors are required at every transceiver pin, placed within 200 mils of the BGA ball. Recommend Intel's F40 PCB design guidelines and use the Quartus Prime pin planner with the .bxl board file to verify escape routing before tape-out.
At 17.4 Gbps transceiver rates, channel loss budget is approximately 12 dB at the Nyquist frequency. Use pre-emphasis and equalization settings recommended by Intel for the F40 footprint. Maintain 100-ohm differential impedance with tight skew control (less than 2 ps) across all SERDES pairs. Reference plane transitions should be minimized to avoid impedance discontinuities; if unavoidable, use GND stitching vias every lambda/10. For DDR4 interfaces, perform read/write leveling with the Soft Memory Controller and validate timing margins across voltage and temperature corners.
The 10AX115N2F40E2LG requires multiple supply rails: 0.9 V SmartVID core, 1.2 V auxiliary, 1.8 V I/O and transceiver analog, and 2.5 V/3.0 V for general I/O banks. Use a Power Management IC with sequencing, such as the Intel Enpirion EM2130 or equivalent. Decoupling must include bulk capacitors (470 uF polymer or tantalum) plus 0.1 uF, 1 uF, and 10 uF ceramic capacitors near each power pin. SmartVID voltage must be controlled by a dedicated controller that adjusts the core voltage based on device temperature and performance state.
Common pitfalls with the 10AX115N2F40E2LG include: (1) using the wrong configuration mode (verify JTAG/AS/FPP for your design); (2) missing the MSEL pins settings for Active Serial or Fast Passive Parallel mode; (3) failing to apply proper POR (power-on-reset) timing per Intel guidelines; (4) using outdated Quartus Prime version that does not recognize the -2 speed grade; (5) neglecting the SmartVID voltage ramp profile, which can cause startup failures. Always validate with the latest Intel Arria 10 device errata document before committing to PCB layout.
Compliance Information
RoHS compliant per Arrow product listing. Intel Arria 10 devices are not AEC-Q100 qualified (industrial/consumer grade only). For medical applications, refer to the Intel medical-grade FPGA documentation. The halogen-free status was not present in the verified web data.
