10CL006YE144C6G - Cyclone 10 LP 6K LEs FPGA | Intel | 144-EQFP
MPN: 10CL006YE144C6G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.99 | $11.99 |
| 10 | $10.79 | $107.90 |
| 100 | $9.59 | $959.00 |
| 500 | $8.95 | $4,475.00 |
| 1,000 | $8.15 | $8,150.00 |
Drop-in alternatives for 10CL006YE144C6G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL006YE144A7G
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View Datasheet β10CL006YE144C8G
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View Datasheet β10CL010YE144C6G
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View Datasheet β10CL016YE144C6G
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View Datasheet β10CL025YE144C6G
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View Datasheet β10CL006YE144C6G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 LP |
| Family | 10CL006 |
| Logic Elements (LEs) | 6,272 |
| Embedded Memory | 276,480 bits |
| Embedded Multipliers (18x18) | 15 |
| User I/Os | 88 |
| PLLs | 2 |
| Maximum User I/O Pins | 88 |
| Package | 144-LQFP Exposed Pad (EQFP-144) |
| Mounting Type | Surface Mount |
| Core Voltage | 1.0 V |
| I/O Bank Voltages Supported | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Process Technology | 60 nm low-power CMOS |
| Operating Temperature | 0C to +85C (Commercial) |
| RoHS Status | Compliant |
10CL006YE144C6G Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (bank 1) |
| Pin 2 | I/O β General-purpose user I/O (bank 1) |
| Pin 3 | I/O β General-purpose user I/O (bank 1) |
| Pin 4 | I/O β General-purpose user I/O (bank 1) |
| Pin 5 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 6 | I/O β General-purpose user I/O (bank 1) |
| Pin 7 | I/O β General-purpose user I/O (bank 1) |
| Pin 8 | I/O β General-purpose user I/O (bank 1) |
| Pin 9 | I/O β General-purpose user I/O (bank 1) |
| Pin 10 | I/O β General-purpose user I/O (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β General-purpose user I/O (bank 1) |
| Pin 13 | I/O β General-purpose user I/O (bank 1) |
| Pin 14 | I/O β General-purpose user I/O (bank 1) |
| Pin 15 | I/O β General-purpose user I/O (bank 1) |
| Pin 16 | I/O β General-purpose user I/O (bank 1) |
| Pin 17 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 18 | I/O β General-purpose user I/O (bank 1) |
| Pin 19 | I/O β General-purpose user I/O (bank 1) |
| Pin 20 | I/O β General-purpose user I/O (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β General-purpose user I/O (bank 2) |
| Pin 23 | I/O β General-purpose user I/O (bank 2) |
| Pin 24 | I/O β General-purpose user I/O (bank 2) |
| Pin 25 | I/O β General-purpose user I/O (bank 2) |
| Pin 26 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 27 | I/O β General-purpose user I/O (bank 2) |
| Pin 28 | I/O β General-purpose user I/O (bank 2) |
| Pin 29 | I/O β General-purpose user I/O (bank 2) |
| Pin 30 | I/O β General-purpose user I/O (bank 2) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β General-purpose user I/O (bank 2) |
| Pin 33 | I/O β General-purpose user I/O (bank 2) |
| Pin 34 | I/O β General-purpose user I/O (bank 2) |
| Pin 35 | I/O β General-purpose user I/O (bank 2) |
| Pin 36 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 37 | I/O β General-purpose user I/O (bank 2) |
| Pin 38 | I/O β General-purpose user I/O (bank 2) |
| Pin 39 | I/O β General-purpose user I/O (bank 2) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β General-purpose user I/O (bank 3) |
| Pin 42 | I/O β General-purpose user I/O (bank 3) |
| Pin 43 | I/O β General-purpose user I/O (bank 3) |
| Pin 44 | I/O β General-purpose user I/O (bank 3) |
| Pin 45 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 46 | I/O β General-purpose user I/O (bank 3) |
| Pin 47 | I/O β General-purpose user I/O (bank 3) |
| Pin 48 | I/O β General-purpose user I/O (bank 3) |
| Pin 49 | I/O β General-purpose user I/O (bank 3) |
| Pin 50 | I/O β General-purpose user I/O (bank 3) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β General-purpose user I/O (bank 3) |
| Pin 53 | I/O β General-purpose user I/O (bank 3) |
| Pin 54 | I/O β General-purpose user I/O (bank 3) |
| Pin 55 | I/O β General-purpose user I/O (bank 3) |
| Pin 56 | I/O β General-purpose user I/O (bank 3) |
| Pin 57 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 58 | I/O β General-purpose user I/O (bank 3) |
| Pin 59 | I/O β General-purpose user I/O (bank 3) |
| Pin 60 | I/O β General-purpose user I/O (bank 3) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β General-purpose user I/O (bank 4) |
| Pin 63 | I/O β General-purpose user I/O (bank 4) |
| Pin 64 | I/O β General-purpose user I/O (bank 4) |
| Pin 65 | I/O β General-purpose user I/O (bank 4) |
| Pin 66 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 67 | I/O β General-purpose user I/O (bank 4) |
| Pin 68 | I/O β General-purpose user I/O (bank 4) |
| Pin 69 | I/O β General-purpose user I/O (bank 4) |
| Pin 70 | I/O β General-purpose user I/O (bank 4) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β General-purpose user I/O (bank 4) |
| Pin 73 | I/O β General-purpose user I/O (bank 4) |
| Pin 74 | I/O β General-purpose user I/O (bank 4) |
| Pin 75 | I/O β General-purpose user I/O (bank 4) |
| Pin 76 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 77 | I/O β General-purpose user I/O (bank 4) |
| Pin 78 | I/O β General-purpose user I/O (bank 4) |
| Pin 79 | I/O β General-purpose user I/O (bank 4) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β General-purpose user I/O (bank 5) |
| Pin 82 | I/O β General-purpose user I/O (bank 5) |
| Pin 83 | I/O β General-purpose user I/O (bank 5) |
| Pin 84 | I/O β General-purpose user I/O (bank 5) |
| Pin 85 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 86 | I/O β General-purpose user I/O (bank 5) |
| Pin 87 | I/O β General-purpose user I/O (bank 5) |
| Pin 88 | I/O β General-purpose user I/O (bank 5) |
| Pin 89 | I/O β General-purpose user I/O (bank 5) |
| Pin 90 | I/O β General-purpose user I/O (bank 5) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β General-purpose user I/O (bank 5) |
| Pin 93 | I/O β General-purpose user I/O (bank 5) |
| Pin 94 | I/O β General-purpose user I/O (bank 5) |
| Pin 95 | I/O β General-purpose user I/O (bank 5) |
| Pin 96 | I/O β General-purpose user I/O (bank 5) |
| Pin 97 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 98 | I/O β General-purpose user I/O (bank 5) |
| Pin 99 | I/O β General-purpose user I/O (bank 5) |
| Pin 100 | I/O β General-purpose user I/O (bank 5) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β General-purpose user I/O (bank 6) |
| Pin 103 | I/O β General-purpose user I/O (bank 6) |
| Pin 104 | I/O β General-purpose user I/O (bank 6) |
| Pin 105 | I/O β General-purpose user I/O (bank 6) |
| Pin 106 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 107 | I/O β General-purpose user I/O (bank 6) |
| Pin 108 | I/O β General-purpose user I/O (bank 6) |
| Pin 109 | I/O β General-purpose user I/O (bank 6) |
| Pin 110 | I/O β General-purpose user I/O (bank 6) |
| Pin 111 | I/O β General-purpose user I/O (bank 6) |
| Pin 112 | GND β Ground |
| Pin 113 | I/O β General-purpose user I/O (bank 6) |
| Pin 114 | I/O β General-purpose user I/O (bank 6) |
| Pin 115 | I/O β General-purpose user I/O (bank 6) |
| Pin 116 | I/O β General-purpose user I/O (bank 6) |
| Pin 117 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 118 | I/O β General-purpose user I/O (bank 6) |
| Pin 119 | I/O β General-purpose user I/O (bank 6) |
| Pin 120 | I/O β General-purpose user I/O (bank 6) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β General-purpose user I/O (bank 7) |
| Pin 123 | I/O β General-purpose user I/O (bank 7) |
| Pin 124 | I/O β General-purpose user I/O (bank 7) |
| Pin 125 | I/O β General-purpose user I/O (bank 7) |
| Pin 126 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 127 | I/O β General-purpose user I/O (bank 7) |
| Pin 128 | I/O β General-purpose user I/O (bank 7) |
| Pin 129 | I/O β General-purpose user I/O (bank 7) |
| Pin 130 | I/O β General-purpose user I/O (bank 7) |
| Pin 131 | GND β Ground |
| Pin 132 | I/O β General-purpose user I/O (bank 7) |
| Pin 133 | I/O β General-purpose user I/O (bank 7) |
| Pin 134 | I/O β General-purpose user I/O (bank 7) |
| Pin 135 | I/O β General-purpose user I/O (bank 7) |
| Pin 136 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 137 | I/O β General-purpose user I/O (bank 7) |
| Pin 138 | I/O β General-purpose user I/O (bank 7) |
| Pin 139 | I/O β General-purpose user I/O (bank 7) |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β General-purpose user I/O (bank 8) |
| Pin 142 | I/O β General-purpose user I/O (bank 8) |
| Pin 143 | I/O β General-purpose user I/O (bank 8) |
| Pin 144 | I/O β General-purpose user I/O (bank 8) |
| Pin EP | GND (Exposed Pad) β Thermal and ground pad, must be soldered to PCB ground pour |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL006YE144C6G is suitable for 6 applications: Industrial Motor Control and FOC Drives, Human-Machine Interface (HMI) Panels, Low-Power Video Processing and Surveillance, IoT Edge Nodes with Custom Sensor Aggregation, Automotive Body Electronics and Infotainment, Portable Medical Monitoring Devices.
Industrial Motor Control and FOC Drives
The Intel 10CL006YE144C6G fits industrial motor control applications requiring field-oriented control (FOC) loops, encoder feedback decoding, and high-resolution PWM generation. Its 15 embedded 18x18 multipliers handle the multiply-intensive FOC math (Clarke, Park, inverse Park transforms) at typical 10-20 kHz control loops with comfortable margin. The 2 integrated PLLs synthesize jitter-clean clocks for 12-16 bit PWM at 50-100 kHz carrier frequencies, while the 88 user I/Os interface directly to Hall sensors, incremental encoders, and gate drivers without external logic. The 144-EQFP package exposes a thermal pad that can be soldered to a ground pour for sustained operation at moderate ambient temperatures in cabinet-mount drives.
Recommended
Human-Machine Interface (HMI) Panels
Industrial HMI panels with TFT-LCD displays, touch controllers, and multiple communication ports leverage the 10CL006YE144C6G to consolidate glue logic that would otherwise require a microcontroller plus several peripheral ICs. The 6,272 LEs implement custom graphics acceleration, double-buffered frame management, and Modbus/CAN/Ethernet protocol stacks concurrently. The 276 Kbits of embedded memory hold lookup tables for fonts and icons, and the 88 user I/Os drive RGB LCD interfaces up to 7-inch WVGA without external bus multiplexers. The commercial 0-85C temperature range covers most factory-floor enclosures, while the EQFP-144 package simplifies optical inspection during high-volume assembly.
Recommended
Low-Power Video Processing and Surveillance
The 10CL006YE144C6G suits entry-level surveillance and consumer video processing where low power consumption and small footprint are essential. Its LUT-based architecture performs real-time image preprocessing (filtering, motion detection, color space conversion) at VGA to 720p resolutions, while the 15 DSP multipliers accelerate convolution kernels for edge detection. The 88 user I/Os interface directly to CMOS image sensors (parallel DVP) and to external DDR2/LPDDR2 memory via soft IP for frame buffering. Quiescent power scales with clock gating, and the 1.0V core supply combined with 60 nm process keeps thermal dissipation low enough for sealed IP camera enclosures.
Recommended
IoT Edge Nodes with Custom Sensor Aggregation
Battery-powered IoT edge nodes benefit from the Cyclone 10 LP's low static power and the 10CL006YE144C6G's flexibility to aggregate heterogeneous sensor buses (I2C, SPI, UART, 1-Wire, custom protocols) into a unified data stream. The 6,272 LEs implement protocol conversion, sensor-fusion preprocessing, and edge analytics, while the 2 PLLs derive multiple precise sample-rate clocks from a single low-frequency crystal. The 88 user I/Os directly interface to many sensors without external I/O expanders, and the 144-EQFP package with exposed pad supports reflow profiles compatible with standard SMT lines. This combination suits smart agriculture, environmental monitoring, and asset-tracking gateways.
Recommended
Automotive Body Electronics and Infotainment
The 10CL006YE144C6G serves automotive body electronics subsystems such as body control modules, LED matrix drivers, and entry-level infotainment I/O hubs. Its 6,272 LEs implement CAN/LIN protocol stacks, multi-zone LED lighting control with per-channel PWM dimming, and HVAC sensor multiplexing. The 88 user I/Os interface directly to automotive switch panels, rotary encoders, and discrete LED drivers. While this commercial 0-85C variant is suitable for cabin-mounted modules, the pin-compatible industrial-temperature 10CL006YE144A7G variant (-40C to +125C) is recommended for under-hood or door-module mounting. The exposed pad simplifies thermal dissipation in sealed automotive enclosures.
Recommended
Portable Medical Monitoring Devices
Portable medical monitoring equipment such as pulse oximeters, ambulatory ECG recorders, and wearable patient monitors benefit from the 10CL006YE144C6G's combination of low power, abundant DSP resources, and small footprint. The 15 embedded 18x18 multipliers accelerate real-time digital filtering of biopotential signals (bandpass, notch, FFT), while the 6,272 LEs implement patient-specific algorithm calibration. The 88 user I/Os interface to AFE ICs (such as the ADS129x family) and to small TFT or OLED displays for patient readouts. The 1.0V core supply minimizes battery drain, extending operating life in continuous-wear applications.
Recommended
Recommended Products Summary
Engineering reference data for 10CL006YE144C6G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL006YE144A7G | 10CL006YE144C8G | 10CL010YE144C6G | 10CL016YE144C6G |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 144-LQFP Exposed Pad (EQFP-144) | 144-LQFP Exposed Pad (EQFP-144) - same | 144-LQFP Exposed Pad (EQFP-144) - same | 144-LQFP Exposed Pad (EQFP-144) - same | 144-LQFP Exposed Pad (EQFP-144) - same |
| Logic Elements | 6,272 | 6,272 | 6,272 | 10,320 | 15,408 |
| Embedded Memory (bits) | 276,480 | 276,480 | 276,480 | 423,936 | 516,096 |
| Embedded 18x18 Multipliers | 15 | 15 | 15 | 24 | 56 |
| User I/Os | 88 | 88 | 88 | 88 | 88 |
| Operating Temperature | 0C to +85C (Commercial) | -40C to +125C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Speed Grade | 6 | 7 | 8 (slower) | 6 | 6 |
Key Differentiators
- Lowest unit cost among Cyclone 10 LP E144 commercial variants (vs 10CL010YE144C6G)
- Smaller LE count but identical footprint to higher-density siblings (vs 10CL016YE144C6G)
- Commercial temperature grade suitable for indoor applications (vs 10CL006YE144A7G)
Design Notes
The Cyclone 10 LP 10CL006 requires a tightly regulated 1.0V core supply with peak current up to approximately 500 mA during configuration and active DSP operation. Use a low-dropout regulator such as the TI TPS74401 or a switching converter with output ripple below 30 mVpp. Power sequencing must drive VCCINT (1.0V core) before or simultaneously with VCCIO (1.2-3.3V I/O banks); violating this order can trigger I/O latch-up and permanent damage. Decouple each VCCIO pin with a 0.1uF X7R ceramic placed within 3 mm of the pin, and add a 10uF bulk capacitor near the package.
Although the EQFP-144 package is not designed for high-power dissipation, the exposed pad must be soldered to a PCB ground pour of at least 25 mm squared to provide thermal relief and a low-inductance ground reference. Estimated: with theta_JA around 25 C/W on a 4-layer JEDEC test board, the device can dissipate roughly 2W continuously at 85C ambient without exceeding the 100C junction limit. Avoid placing the FPGA directly above heat-generating components (DC-DC converters, power inductors) on the PCB, and consider thermal vias under the exposed pad for improved heat transfer to inner copper planes.
Route all high-speed differential pairs (LVDS, RSDS, mini-LVDS) with 100 ohm differential impedance and matched length within 150 mils (about 4 mm) to avoid skew-induced jitter. Keep clock traces short and use the FPGA's dedicated CLK inputs for global clocks; avoid using regular I/O as clock inputs. JTAG signals (TCK, TMS, TDI, TDO) should be routed with ground guard traces to prevent programming failures. Maintain a solid ground plane under the device with stitched ground vias around the perimeter to minimize return-path inductance.
Common pitfalls when designing with the 10CL006YE144C6G include: (1) leaving I/O banks unpowered, which causes leakage current and configuration failure; (2) omitting the CONFIG_DONE pull-up resistor on the configuration pin; (3) using incorrect AS/PS/JTAG mode selection in the Quartus Prime programmer; (4) failing to set unused pins as 'As input tri-stated' in the Quartus pin planner, leading to supply current spikes; (5) using the commercial variant in industrial temperature environments without verifying the device's full operating range. Always run TimeQuest timing analysis after compilation and verify pin assignments against the device handbook pin-out file.
Compliance Information
RoHS and REACH compliance per Intel Cyclone 10 LP product declaration. Lead-free matte tin finish over NiPd underlayer, suitable for 260C peak reflow per JEDEC J-STD-020. Not AEC-Q100 qualified - for automotive applications consult the Intel automotive-grade FPGA portfolio (Cyclone V Auto, Arria V Auto).
