10CL010ZE144I8G - Cyclone 10 LP FPGA, 10K LE, 144-EQFP | Intel
MPN: 10CL010ZE144I8G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $26.8 | $2,680.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $19.6 | $19,600.00 |
Drop-in alternatives for 10CL010ZE144I8G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL010YE144I7G
β Drop-Inβ In Stock
$17.9 / Unit
View Datasheet β10CL010YE144C8G
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet β10CL006ZE144I8G
β Drop-Inβ In Stock
$35.88 / Unit
View Datasheet β10CL006ZE144I8G
β Drop-Inβ In Stock
$35.88 / Unit
View Datasheet β10CL010ZE144I8G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 LP |
| Logic Elements (LE) | 10,320 |
| Embedded Memory | 423,936 bits (414 Kbit) |
| Embedded 18x18 Multipliers | 46 |
| User I/O Pins | 88 |
| PLLs | 4 |
| Global Clock Networks | 20 |
| Package | 144-pin EQFP (LQFP with exposed pad) |
| Operating Temperature | -40C to +100C (Industrial, 'I' suffix) |
| Speed Grade | 8 (commercial speed grade mapping) |
| Process Node | 60 nm low-power |
| Core Voltage | 1.0 V (typical), 1.2 V option |
| Configuration Method | JTAG, Serial Passive (PS), Serial Active (AS) |
| RoHS Status | Compliant |
| Programming Software | Intel Quartus Prime Lite / Standard |
10CL010ZE144I8G Pin Configuration
| Pin 1 | I/O β General purpose user I/O bank 1 |
| Pin 2 | I/O β General purpose user I/O bank 1 |
| Pin 3 | I/O β General purpose user I/O bank 1 |
| Pin 4 | I/O β General purpose user I/O bank 1 |
| Pin 5 | I/O β General purpose user I/O bank 1 |
| Pin 6 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 7 | I/O β General purpose user I/O bank 1 |
| Pin 8 | I/O β General purpose user I/O bank 1 |
| Pin 9 | I/O β General purpose user I/O bank 1 |
| Pin 10 | I/O β General purpose user I/O bank 1 |
| Pin 11 | I/O β General purpose user I/O bank 2 |
| Pin 12 | I/O β General purpose user I/O bank 2 |
| Pin 13 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 14 | I/O β General purpose user I/O bank 2 |
| Pin 15 | I/O β General purpose user I/O bank 2 |
| Pin 16 | I/O β General purpose user I/O bank 2 |
| Pin 17 | I/O β General purpose user I/O bank 2 |
| Pin 18 | I/O β General purpose user I/O bank 2 |
| Pin 19 | I/O β General purpose user I/O bank 3 |
| Pin 20 | I/O β General purpose user I/O bank 3 |
| Pin 21 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 22 | I/O β General purpose user I/O bank 3 |
| Pin 23 | I/O β General purpose user I/O bank 3 |
| Pin 24 | I/O β General purpose user I/O bank 3 |
| Pin 25 | I/O β General purpose user I/O bank 3 |
| Pin 26 | I/O β General purpose user I/O bank 3 |
| Pin 27 | I/O β General purpose user I/O bank 4 |
| Pin 28 | I/O β General purpose user I/O bank 4 |
| Pin 29 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 30 | I/O β General purpose user I/O bank 4 |
| Pin 31 | I/O β General purpose user I/O bank 4 |
| Pin 32 | I/O β General purpose user I/O bank 4 |
| Pin 33 | I/O β General purpose user I/O bank 4 |
| Pin 34 | I/O β General purpose user I/O bank 4 |
| Pin 35 | I/O β General purpose user I/O bank 5 |
| Pin 36 | I/O β General purpose user I/O bank 5 |
| Pin 37 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 38 | I/O β General purpose user I/O bank 5 |
| Pin 39 | I/O β General purpose user I/O bank 5 |
| Pin 40 | I/O β General purpose user I/O bank 5 |
| Pin 41 | I/O β General purpose user I/O bank 5 |
| Pin 42 | I/O β General purpose user I/O bank 5 |
| Pin 43 | I/O β General purpose user I/O bank 6 |
| Pin 44 | I/O β General purpose user I/O bank 6 |
| Pin 45 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 46 | I/O β General purpose user I/O bank 6 |
| Pin 47 | I/O β General purpose user I/O bank 6 |
| Pin 48 | I/O β General purpose user I/O bank 6 |
| Pin 49 | I/O β General purpose user I/O bank 6 |
| Pin 50 | I/O β General purpose user I/O bank 6 |
| Pin 51 | I/O β General purpose user I/O bank 7 |
| Pin 52 | I/O β General purpose user I/O bank 7 |
| Pin 53 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 54 | I/O β General purpose user I/O bank 7 |
| Pin 55 | I/O β General purpose user I/O bank 7 |
| Pin 56 | I/O β General purpose user I/O bank 7 |
| Pin 57 | I/O β General purpose user I/O bank 7 |
| Pin 58 | I/O β General purpose user I/O bank 7 |
| Pin 59 | I/O β General purpose user I/O bank 8 |
| Pin 60 | I/O β General purpose user I/O bank 8 |
| Pin 61 | VCCIO8 β I/O bank 8 supply voltage |
| Pin 62 | I/O β General purpose user I/O bank 8 |
| Pin 63 | I/O β General purpose user I/O bank 8 |
| Pin 64 | I/O β General purpose user I/O bank 8 |
| Pin 65 | I/O β General purpose user I/O bank 8 |
| Pin 66 | I/O β General purpose user I/O bank 8 |
| Pin 67 | nSTATUS β Configuration status signal (open-drain) |
| Pin 68 | DCLK β Configuration clock input |
| Pin 69 | DATA0 β Configuration data input |
| Pin 70 | nCONFIG β Configuration active-low reset |
| Pin 71 | CONF_DONE β Configuration done open-drain output |
| Pin 72 | TCK β JTAG clock input |
| Pin 73 | TMS β JTAG mode select input |
| Pin 74 | TDI β JTAG data input |
| Pin 75 | TDO β JTAG data output |
| Pin 76 | MSEL0 β Configuration mode select 0 |
| Pin 77 | MSEL1 β Configuration mode select 1 |
| Pin 78 | MSEL2 β Configuration mode select 2 |
| Pin 79 | nCE β Chip enable (active low, tie low for normal operation) |
| Pin 80 | nCEO β Chip enable output for daisy-chain (leave NC if unused) |
| Pin 81 | CLK0 β Dedicated clock input 0 (single-ended or LVDS positive) |
| Pin 82 | CLK0n β Dedicated clock input 0 negative (LVDS) |
| Pin 83 | CLK1 β Dedicated clock input 1 |
| Pin 84 | CLK1n β Dedicated clock input 1 negative (LVDS) |
| Pin 85 | CLK2 β Dedicated clock input 2 |
| Pin 86 | CLK2n β Dedicated clock input 2 negative (LVDS) |
| Pin 87 | CLK3 β Dedicated clock input 3 |
| Pin 88 | CLK3n β Dedicated clock input 3 negative (LVDS) |
| Pin 89 | I/O β General purpose user I/O |
| Pin 90 | I/O β General purpose user I/O |
| Pin 91 | I/O β General purpose user I/O |
| Pin 92 | I/O β General purpose user I/O |
| Pin 93 | I/O β General purpose user I/O |
| Pin 94 | I/O β General purpose user I/O |
| Pin 95 | I/O β General purpose user I/O |
| Pin 96 | I/O β General purpose user I/O |
| Pin 97 | I/O β General purpose user I/O |
| Pin 98 | I/O β General purpose user I/O |
| Pin 99 | I/O β General purpose user I/O |
| Pin 100 | I/O β General purpose user I/O |
| Pin 101 | I/O β General purpose user I/O |
| Pin 102 | I/O β General purpose user I/O |
| Pin 103 | I/O β General purpose user I/O |
| Pin 104 | I/O β General purpose user I/O |
| Pin 105 | I/O β General purpose user I/O |
| Pin 106 | I/O β General purpose user I/O |
| Pin 107 | I/O β General purpose user I/O |
| Pin 108 | I/O β General purpose user I/O |
| Pin 109 | I/O β General purpose user I/O |
| Pin 110 | I/O β General purpose user I/O |
| Pin 111 | I/O β General purpose user I/O |
| Pin 112 | I/O β General purpose user I/O |
| Pin 113 | I/O β General purpose user I/O |
| Pin 114 | I/O β General purpose user I/O |
| Pin 115 | I/O β General purpose user I/O |
| Pin 116 | I/O β General purpose user I/O |
| Pin 117 | I/O β General purpose user I/O |
| Pin 118 | I/O β General purpose user I/O |
| Pin 119 | I/O β General purpose user I/O |
| Pin 120 | I/O β General purpose user I/O |
| Pin 121 | I/O β General purpose user I/O |
| Pin 122 | I/O β General purpose user I/O |
| Pin 123 | GND β Ground reference |
| Pin 124 | VCCA_PLL β PLL analog supply voltage (2.5 V) |
| Pin 125 | GNDA_PLL β PLL analog ground |
| Pin 126 | VCCD_PLL β PLL digital supply voltage (1.0-1.2 V) |
| Pin 127 | VCCINT β Core logic supply voltage (1.0-1.2 V) |
| Pin 128 | GND β Ground reference |
| Pin 129 | I/O β General purpose user I/O |
| Pin 130 | I/O β General purpose user I/O |
| Pin 131 | I/O β General purpose user I/O |
| Pin 132 | I/O β General purpose user I/O |
| Pin 133 | I/O β General purpose user I/O |
| Pin 134 | I/O β General purpose user I/O |
| Pin 135 | I/O β General purpose user I/O |
| Pin 136 | I/O β General purpose user I/O |
| Pin 137 | I/O β General purpose user I/O |
| Pin 138 | I/O β General purpose user I/O |
| Pin 139 | I/O β General purpose user I/O |
| Pin 140 | I/O β General purpose user I/O |
| Pin 141 | I/O β General purpose user I/O |
| Pin 142 | I/O β General purpose user I/O |
| Pin 143 | I/O β General purpose user I/O |
| Pin 144 | I/O β General purpose user I/O |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL010ZE144I8G is suitable for 6 applications: Industrial Motor Control, Video Bridging and Protocol Conversion, I/O Expansion and Glue Logic, Test and Measurement Equipment, Portable Medical Devices, Low-Cost Software Defined Radio.
Industrial Motor Control
The 10CL010ZE144I8G is well suited for low-cost industrial motor and motion control applications where its 10,320 logic elements, 46 embedded 18x18 multipliers, and 88 user I/Os are sufficient to implement PWM generators, encoder interfaces, and field-oriented control (FOC) loops. The Cyclone 10 LP fabric achieves FOC computation cycles at typical PWM switching frequencies of 10-20 kHz, while the industrial -40C to +100C temperature grade ensures operation in factory environments. Its exposed-pad 144-pin EQFP package simplifies PCB layout by exposing all I/Os on a single side of the chip, easing routing for multi-axis controllers.
Recommended
Video Bridging and Protocol Conversion
The 10CL010ZE144I8G is widely used as a video format converter, capable of bridging between HDMI, MIPI CSI-2, LVDS, and parallel RGB interfaces using external PHY transceivers paired with on-chip logic. Its 423 Kbit of embedded M9K memory is well sized for line buffers and frame synchronization FIFOs in 720p/1080p designs. The 4 PLLs provide independent clock synthesis for each video domain, and the 88 user I/Os allow direct connection to 24/30-bit parallel video buses plus sideband control signals.
Recommended
I/O Expansion and Glue Logic
The 10CL010ZE144I8G serves as a flexible I/O expander for embedded processors and microcontrollers that lack sufficient native peripherals, providing additional UART, SPI, I2C, PWM, and GPIO channels. Its low non-volatile configuration storage and rapid reprogrammability via JTAG allow late-stage design changes without PCB rework. The 60 nm low-power process yields static consumption below 100 mA in typical designs, which is acceptable for always-on industrial equipment where the FPGA serves as auxiliary logic alongside a host CPU.
Recommended
Test and Measurement Equipment
The 10CL010ZE144I8G is used in entry-level bench instruments such as logic analyzers, protocol exercisers, and data acquisition front-ends where its reprogrammable logic supports multi-protocol capture. The 88 user I/Os accommodate multiple synchronous digital input channels sampled by the on-chip PLLs at rates up to 315 MHz in M9K FIFO mode. The 46 embedded 18x18 multipliers enable real-time DSP for FFT pre-processing or digital filtering of acquired waveforms, reducing host CPU burden.
Recommended
Portable Medical Devices
The 10CL010ZE144I8G is appropriate for portable medical electronics such as patient monitoring peripherals, infusion pump controllers, and diagnostic instrument interfaces where its low static power and small EQFP package meet portable form-factor constraints. The industrial temperature grade covers clinical environment requirements, and the 414 Kbit of embedded memory supports local waveform buffering without external SRAM. The exposed thermal pad allows fanless operation, critical for sealed medical enclosures where airflow is not available.
Recommended
Low-Cost Software Defined Radio
The 10CL010ZE144I8G implements digital downconversion, channelization, and baseband processing in entry-level software defined radio receivers and signal intelligence applications. Its 46 embedded 18x18 multipliers perform complex FFT operations, while the M9K memory blocks store time-domain samples and pre-computed twiddle factors. The LVDS-capable I/Os interface directly to ADC/DAC chips such as the AD9643, enabling sub-$200 single-board SDR designs for amateur radio, university labs, and industrial spectrum monitoring.
Recommended
Recommended Products Summary
Engineering reference data for 10CL010ZE144I8G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL010YE144I7G | 10CL010YE144C8G | 10CL006ZE144I8G |
|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera |
| Package | 144-pin EQFP | 144-pin EQFP - same | 144-pin EQFP - same | 144-pin EQFP - same |
| Logic Elements | 10,320 | 10,320 | 10,320 | 6,272 (-39%) |
| Embedded Memory | 423,936 bits | 423,936 bits | 423,936 bits | 270,336 bits (-36%) |
| User I/Os | 88 | 88 | 88 | 88 |
| Embedded Multipliers (18x18) | 46 | 46 | 46 | 30 (-35%) |
| PLLs | 4 | 4 | 4 | 2 (-50%) |
| Temperature Grade | Industrial -40C to +100C | Industrial -40C to +100C | Commercial 0C to +85C | Industrial -40C to +100C |
| Speed Grade | 8 | 7 (faster) | 8 | 8 |
Key Differentiators
- Lowest-density Cyclone 10 LP member with full EQFP-144 pin-out (vs 10CL006ZE144I8G)
- Industrial temperature grade with full-speed operation (vs 10CL010YE144C8G)
- Four PLLs versus only two in 10CL006 density grade (vs 10CL006ZE144I8G)
Design Notes
The 144-pin EQFP package's exposed thermal pad MUST be soldered to a PCB ground copper pour of at least 1 square inch (6.45 cm^2) to achieve the datasheet thermal performance of approximately 28 C/W theta_JA. Without proper thermal pad soldering, the junction temperature can rise above the 100C industrial limit during sustained high-utilization designs (90%+ LE utilization at 100 MHz). Add thermal vias in a 4x4 grid under the exposed pad to conduct heat into internal ground planes.
Estimated: Power consumption for a typical 10CL010ZE144I8G design at 70% LE utilization and 100 MHz toggle rate is approximately 0.5-0.8 W. Decouple each VCCIO bank with a 0.1 uF ceramic capacitor placed within 5 mm of the bank supply pin, and provide a 10 uF bulk capacitor on each of VCCINT, VCCA_PLL, and VCCD_PLL rails. PLLs require a separate filtered analog supply (typically a ferrite bead in series with VCCA_PLL) to minimize jitter.
Route JTAG signals TCK, TMS, TDI, TDO with 4 mil traces and keep them short (under 50 mm total length) to avoid configuration failures during programming. Pull nCONFIG up to 3.3 V via 10 kohm resistor, and leave nCEO unconnected (NC) for single-device configurations. Place the configuration flash (EPCS or compatible serial NOR) within 25 mm of the FPGA DATA0/DCLK pins, with 50 ohm controlled impedance routing to minimize signal integrity issues at 40 MHz DCLK.
Do NOT leave unused I/O pins floating - configure them as outputs driving ground in the Quartus pin planner, or as inputs with internal weak pull-up enabled. Floating unused inputs cause excessive Icc current and may trigger CRC errors during operation. Also, ensure MSEL[2:0] pins are tied to the correct logic levels matching your chosen configuration mode (AS=010, PS=000, JTAG=101) before power-up; incorrect MSEL settings cause configuration failure.
Compliance Information
RoHS and lead-free per Intel product page. Not AEC-Q100 qualified - the Cyclone 10 LP family targets industrial, not automotive safety-critical applications.
