10CL016YM164C8G - Cyclone 10 LP FPGA, 15K LE, 164-MBGA | Intel
MPN: 10CL016YM164C8G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.4 | $254.00 |
| 100 | $21.95 | $2,195.00 |
| 500 | $19.2 | $9,600.00 |
| 1,000 | $17.1 | $17,100.00 |
Drop-in alternatives for 10CL016YM164C8G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL016YM164C6G
β Drop-Inβ In Stock
$18.4 / Unit
View Datasheet β10CL016YM164A7G
β Drop-Inβ In Stock
$16.75 / Unit
View Datasheet β10CL016YM164A7G
β Drop-Inβ In Stock
$16.75 / Unit
View Datasheet β10CL016YM164C8G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 LP |
| Device Family | 10CL016 |
| Logic Elements (LE) | 15,408 |
| Adaptive Logic Modules (ALM) | 9,638 |
| Embedded Memory (bits) | 516,096 (504 kbit M9K blocks) |
| Embedded Multipliers (18x18) | 56 |
| User I/Os | 87 |
| PLLs | 2 (general-purpose) |
| Configuration Schemes | JTAG, AS (serial), PS (passive) |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) |
| Core Voltage (VCCINT) | 1.2 V |
| I/O Bank Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| PLL Analog Voltage (VCCA_PLL) | 2.5 V |
| Package | 164-MBGA (M164), 8 x 8 mm, 0.5 mm pitch |
| Mounting Type | Surface Mount |
| MSL Level | MSL-3 per JEDEC J-STD-020 |
| RoHS Status | Compliant |
| Speed Grade | C8 (commercial, 8 speed grade) |
| Process Node | 60 nm low-power |
| Design Software | Intel Quartus Prime Lite/Standard/Pro |
10CL016YM164C8G Pin Configuration
| Pin A1 | IO β User I/O (bank 1A) |
| Pin A2 | IO β User I/O (bank 1A) |
| Pin A3 | VCCIO1A β I/O bank 1A supply |
| Pin A4 | IO β User I/O (bank 1A) |
| Pin A5 | IO β User I/O (bank 1A) |
| Pin A6 | GND β Ground |
| Pin A7 | IO β User I/O (bank 2A) |
| Pin A8 | VCCIO2A β I/O bank 2A supply |
| Pin A9 | IO β User I/O (bank 2A) |
| Pin A10 | IO β User I/O (bank 2A) |
| Pin A11 | VCCINT β Core 1.2 V supply |
| Pin B1 | GND β Ground |
| Pin B2 | IO β User I/O (bank 1A) |
| Pin B3 | IO β User I/O (bank 1A) |
| Pin B4 | VCCIO1B β I/O bank 1B supply |
| Pin B5 | IO β User I/O (bank 1B) |
| Pin B6 | VCCIO1B β I/O bank 1B supply |
| Pin B7 | IO β User I/O (bank 2A) |
| Pin B8 | IO β User I/O (bank 2A) |
| Pin B9 | VCCIO2B β I/O bank 2B supply |
| Pin B10 | IO β User I/O (bank 2B) |
| Pin B11 | GND β Ground |
| Pin C1 | IO β User I/O (bank 1A) |
| Pin C2 | VCCINT β Core 1.2 V supply |
| Pin C3 | IO β User I/O (bank 1A) |
| Pin C4 | IO β User I/O (bank 1A) |
| Pin C5 | IO β User I/O (bank 1B) |
| Pin C6 | IO β User I/O (bank 1B) |
| Pin C7 | IO β User I/O (bank 2B) |
| Pin C8 | IO β User I/O (bank 2B) |
| Pin C9 | IO β User I/O (bank 2B) |
| Pin C10 | VCCINT β Core 1.2 V supply |
| Pin C11 | IO β User I/O (bank 2B) |
| Pin D1 | IO β User I/O (bank 3A) |
| Pin D2 | IO β User I/O (bank 3A) |
| Pin D3 | GND β Ground |
| Pin D4 | TMS β JTAG test mode select |
| Pin D5 | TCK β JTAG test clock |
| Pin D6 | nCONFIG β Configuration control (active-low) |
| Pin D7 | MSEL0 β Configuration mode select 0 |
| Pin D8 | MSEL1 β Configuration mode select 1 |
| Pin D9 | GND β Ground |
| Pin D10 | IO β User I/O (bank 4A) |
| Pin D11 | IO β User I/O (bank 4A) |
| Pin E1 | VCCIO3A β I/O bank 3A supply |
| Pin E2 | IO β User I/O (bank 3A) |
| Pin E3 | IO β User I/O (bank 3A) |
| Pin E4 | TDI β JTAG test data in |
| Pin E5 | nSTATUS β Configuration status (active-low) |
| Pin E6 | MSEL2 β Configuration mode select 2 |
| Pin E7 | DCLK β Configuration clock (AS/PS modes) |
| Pin E8 | TDO β JTAG test data out |
| Pin E9 | IO β User I/O (bank 4A) |
| Pin E10 | IO β User I/O (bank 4A) |
| Pin E11 | VCCIO4A β I/O bank 4A supply |
| Pin F1 | IO β User I/O (bank 3A) |
| Pin F2 | VCCINT β Core 1.2 V supply |
| Pin F3 | IO β User I/O (bank 3A) |
| Pin F4 | nCE β Chip enable (active-low) |
| Pin F5 | CONFIG_DONE β Configuration complete status |
| Pin F6 | DATA0 β Configuration data 0 |
| Pin F7 | CRC_ERROR β Configuration CRC error indicator |
| Pin F8 | IO β User I/O (bank 4B) |
| Pin F9 | IO β User I/O (bank 4B) |
| Pin F10 | VCCINT β Core 1.2 V supply |
| Pin F11 | IO β User I/O (bank 4B) |
| Pin G1 | GND β Ground |
| Pin G2 | IO β User I/O (bank 3B) |
| Pin G3 | VCCIO3B β I/O bank 3B supply |
| Pin G4 | PLL1_CLKOUTp β PLL1 clock output positive |
| Pin G5 | VCCA_PLL1 β PLL1 analog 2.5 V supply |
| Pin G6 | GNDA_PLL1 β PLL1 analog ground |
| Pin G7 | PLL2_CLKOUTp β PLL2 clock output positive |
| Pin G8 | VCCIO4B β I/O bank 4B supply |
| Pin G9 | IO β User I/O (bank 4B) |
| Pin G10 | IO β User I/O (bank 4B) |
| Pin G11 | GND β Ground |
| Pin H1 | IO β User I/O (bank 3B) |
| Pin H2 | IO β User I/O (bank 3B) |
| Pin H3 | IO β User I/O (bank 3B) |
| Pin H4 | VCCA_PLL2 β PLL2 analog 2.5 V supply |
| Pin H5 | GNDA_PLL2 β PLL2 analog ground |
| Pin H6 | PLL1_CLKp β PLL1 clock input positive |
| Pin H7 | PLL2_CLKp β PLL2 clock input positive |
| Pin H8 | IO β User I/O (bank 4B) |
| Pin H9 | IO β User I/O (bank 4B) |
| Pin H10 | IO β User I/O (bank 4B) |
| Pin H11 | VCCIO4B β I/O bank 4B supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL016YM164C8G is suitable for 6 applications: Industrial Motor Control and Drive Interface, Machine Vision and Image Pre-Processing, Video Bridging and Display Conversion, Software-Defined Radio (SDR) Front-End Glue Logic, Sensor Aggregation and Industrial IoT Gateway, Consumer Electronics Glue Logic and Display Controllers.
Industrial Motor Control and Drive Interface
The 10CL016YM164C8G fits industrial motor-control designs because its 56 (18x18) hardware multipliers accelerate field-oriented-control (FOC) loops, and the two general-purpose PLLs generate the precise switching frequencies required for IGBT and SiC gate-driver timing. With 15,408 LE the device can host an entire FOC + space-vector PWM core plus encoder resolver interfaces, while the 87 I/Os comfortably connect to multi-axis feedback (QEP, Hall, BISS, ENDAT). The 1.2 V core plus per-bank VCCIO makes interfacing to 3.3 V gate drivers and 5 V sensors straightforward. Power dissipation is moderate thanks to the 60 nm low-power process, allowing convection cooling in control cabinets. Drop-in replacement with 10CL016YM164A7G for AEC-Q100 automotive traction inverters.
Recommended
Machine Vision and Image Pre-Processing
For machine-vision preprocessing at the edge, the 10CL016YM164C8G delivers 504 kbit of embedded M9K memory to buffer line-scan image data and 15,408 LE to implement Bayer-to-RGB demosaic, Gaussian filtering, and Sobel edge detection in hardware. The 87 I/Os enable direct connection to MIPI-CSI or parallel CMOS image sensors plus an LVDS output to a host SoC. The Cyclone 10 LP low-power architecture keeps thermal envelope under 2 W typical, suitable for fanless industrial cameras. Cyclone 10 LP family devices with M164 package are interchangeable in the same PCB footprint, so the same board design can scale from C6 to C8 or A7 speed grades.
Recommended
Video Bridging and Display Conversion
The 10CL016YM164C8G is well-suited to video-bridging applications (HDMI-to-LVDS, MIPI-to-RGB, dual-camera stitching) where its 15,408 LE plus 56 hardware multipliers handle color-space conversion and scaling algorithms at 1080p60 with headroom. The 8 I/O banks with mixed VCCIO (1.2/1.5/1.8/2.5/3.3 V) simplify interfacing legacy parallel LCD, MIPI DSI, and LVDS panels without level shifters. The 504 kbit embedded RAM acts as a two-line buffer for picture cropping and timing conversion. The M164 8x8 mm package is small enough for in-cable dongles and behind-display controller boards. Quartus Prime Lite includes royalty-free IP for HDMI 1.4, MIPI DSI, and I2C/SPI bridges.
Recommended
Software-Defined Radio (SDR) Front-End Glue Logic
The 10CL016YM164C8G serves as a flexible digital front-end in low-cost SDR platforms: the two PLLs derive stable sampling clocks for the ADC/DAC pair, while 15,408 LE implement digital down-conversion (DDC), finite-impulse-response (FIR) filtering, and gain control. The 87 I/Os route digital IQ data plus SPI/I2C control to the RF tuner and host processor. The 60 nm low-power process keeps the FPGA under 1.5 W at typical SDR duty cycles, matching battery-powered QRP radio requirements. The same M164 footprint allows easy migration between commercial and industrial grades per the deployment environment.
Recommended
Sensor Aggregation and Industrial IoT Gateway
The 10CL016YM164C8G aggregates up to ~12 sensor interfaces in industrial IoT gateways: each interface (I2C, SPI, UART, GPIO, Modbus RTU) consumes roughly 1-2 K LE plus a few hardware multipliers for averaging and threshold detection. The 87 I/Os support multiple physical interfaces plus an Ethernet MAC or two RGMII/RMII paths to a host MCU. Two PLLs generate isolated timing references for legacy RS-485 networks. The 504 kbit M9K memory buffers protocol frames before forwarding, reducing host CPU interrupts. The M164 package is small enough for DIN-rail-mounted gateways and supports AEC-Q100 via the A7G grade drop-in for harsh factory environments.
Recommended
Consumer Electronics Glue Logic and Display Controllers
In consumer products (smart appliances, AV receivers, e-bike dashboards, low-end arcade boards), the 10CL016YM164C8G provides the I/O flexibility and timing generation that fixed-function microcontrollers lack: bridging I2S audio to S/PDIF, generating custom PWM for LED drivers, time-multiplexing button matrices, and routing IR remote signals. The 15,408 LE plus 504 kbit of embedded RAM are sufficient for medium-complexity state machines and waveform generation, while the 8x8 mm M164 package fits behind compact displays. The C8 commercial speed grade covers 1080p timing at 148.5 MHz pixel clock with margin. AEC-Q100 migration via A7G is straightforward for shared hardware platforms.
Recommended
Recommended Products Summary
Engineering reference data for 10CL016YM164C8G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL016YM164C6G | 10CL016YM164A7G | 10CL016YM164I7G |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 164-MBGA (M164) 8x8 mm | 164-MBGA (M164) 8x8 mm - same | 164-MBGA (M164) 8x8 mm - same | 164-MBGA (M164) 8x8 mm - same |
| Logic Elements | 15,408 | 15,408 - same | 15,408 - same | 15,408 - same |
| Embedded Memory (bits) | 516,096 (504 kbit) | 516,096 - same | 516,096 - same | 516,096 - same |
| User I/Os | 87 | 87 - same | 87 - same | 87 - same |
| Speed Grade | C8 | C6 (faster Fmax) | A7 (automotive, faster) | I7 (industrial, faster) |
| Operating Temperature | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) | -40 C to +125 C (automotive, AEC-Q100) | -40 C to +100 C (industrial) |
| AEC-Q100 Qualified | No | No | Yes | No (industrial grade) |
| Core Voltage (VCCINT) | 1.2 V | 1.2 V - same | 1.2 V - same | 1.2 V - same |
| Approx. 1-pc Price (USD) | 28.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Smallest Cyclone 10 LP 016 package option (vs 10CL016YF484C8G)
- Same-family drop-in variants cover commercial/industrial/automotive grades (vs 10CL016YM164C8G only)
- Lowest-cost Cyclone 10 LP speed grade in this OPN (vs 10CL016YM164C6G)
Design Notes
Estimated: at 25% toggle rate on 87 I/Os loaded with 8 mA each and full logic utilization, VCCINT current on 10CL016YM164C8G is approximately 350-500 mA from 1.2 V plus 100-200 mA from VCCIO banks. Bulk decoupling should be 22 uF tantalum + 0.1 uF ceramic per supply pin group, plus 1 uF ceramic on every fourth pin; follow the Intel Cyclone 10 LP pin connection guidelines. VCCA_PLL (2.5 V) and GNDA_PLL must be star-grounded to a quiet analog ground plane to meet PLL jitter specifications.
The 164-MBGA package uses a 0.5 mm pitch and is not hand-solderable; use a 4-layer PCB with at least 1 oz copper, micro-via-in-pad or via-in-pad recommended for the BGA fanout. Reflow profile must conform to JEDEC J-STD-020 MSL-3 with peak 260 C, and the package must be baked at 125 C for 24 hours before assembly if the humidity indicator card has exceeded 10% RH equivalent. Ball land pattern is 0.45 mm diameter with NSMD (non-solder-mask-defined) pads for best reliability.
Common pitfalls include: (1) floating MSEL pins must be tied high or low per the desired configuration mode (AS/PS/JTAG) - leaving them floating causes configuration failures; (2) nCONFIG and nSTATUS must be pulled up to 1.8 V (or VCCIO) and not driven by external logic during configuration; (3) VCCIO banks not in use must still be powered to 1.8 V or 2.5 V (not left floating) to avoid leakage on the input buffers; (4) the JTAG chain must include proper TCK termination; (5) avoid sharing VCCIO between banks driving different logic levels - each bank must have its own decoupled rail.
Route differential pairs (LVDS, DDR memory clocks) with 100 ohm differential impedance and match lengths within 150 mil. The two PLLs should be fed from dedicated clock inputs with short, isolated traces; do not route noisy signals under the PLL supply ferrite beads. M9K memory blocks benefit from localized register duplication in HDL; using the LogicLock region feature in Quartus Prime to lock memory placement can reduce routing congestion at the center of the BGA. Leave at least 200 mil clearance between the BGA and any board edge for rework access.
Compliance Information
RoHS/REACH compliant per Intel product page. Not AEC-Q100 - choose 10CL016YM164A7G for AEC-Q100 automotive use. Halogen-free per Intel Cyclone 10 LP family declaration.
