5M160ZM100I5N - MAX V CPLD, 128 Macro Cells, 100-MBGA | Intel
MPN: 5M160ZM100I5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
Drop-in alternatives for 5M160ZM100I5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
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View Datasheet β5M160ZM100I5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device | 5M160Z |
| Logic Elements (Macro Cells) | 128 |
| User I/Os | 79 |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns |
| Internal Performance | 118.3 MHz at 1.8 V |
| Core Voltage | 1.8 V |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V LVCMOS/LVTTL |
| Package | 100-ball MBGA (Micro FineLine BGA) |
| Configuration Memory | Internal flash (non-volatile) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature (Industrial) | -40C to +100C |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (BGA) |
| Design Software | Intel Quartus Prime / Quartus II |
5M160ZM100I5N Pin Configuration
| Pin A1 | I/O β User I/O (bank 1) |
| Pin A2 | I/O β User I/O (bank 1) |
| Pin A3 | I/O β User I/O (bank 1) |
| Pin A4 | I/O β User I/O (bank 1) |
| Pin A5 | I/O β User I/O (bank 1) |
| Pin A6 | I/O β User I/O (bank 1) |
| Pin A7 | VCCIO1 β I/O bank 1 supply |
| Pin A8 | I/O β User I/O (bank 1) |
| Pin A9 | I/O β User I/O (bank 1) |
| Pin A10 | I/O β User I/O (bank 1) |
| Pin B1 | I/O β User I/O (bank 1) |
| Pin B10 | GND β Ground |
| Pin C1 | TDI β JTAG Test Data In |
| Pin C10 | I/O β User I/O (bank 2) |
| Pin D1 | TMS β JTAG Test Mode Select |
| Pin D10 | TCK β JTAG Test Clock |
| Pin E1 | VCCINT β Core 1.8 V supply |
| Pin E10 | TDO β JTAG Test Data Out |
| Pin F1 | GND β Ground |
| Pin F10 | I/O β User I/O (bank 3) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZM100I5N is suitable for 6 applications: Industrial Control and I/O Expansion, Glue Logic and Bus Bridging, Power-Up Sequencing and Supervisory Control, Motor and LED Driving Logic, Low-Power Portable and Battery-Backed Designs, Legacy Interface Adaptation.
Industrial Control and I/O Expansion
The 5M160ZM100I5N is well suited for industrial control boards that require deterministic, instant-on glue logic between a microcontroller and external sensors or actuators. Its 79 user I/Os allow direct fan-out of an MCU's limited GPIO to dozens of optocouplers, relays, and indicator LEDs. The industrial temperature grade (-40C to +100C) covers factory-floor environments. Non-volatile flash configuration means the CPLD comes up in a known valid state within microseconds of power-on, which is critical for safety interlocks and deterministic sequencing. Multi-voltage I/O banks let the same part bridge a 3.3 V sensor network to a 1.8 V Cortex-M host without level shifters, reducing BOM cost. Designers can use Quartus Prime to capture state machines for debouncing, PWM generation, or stepper motor control.
Recommended
Glue Logic and Bus Bridging
In embedded systems that mix legacy parallel buses (8080, ISA-style) with modern serial interfaces (SPI, I2C, UART), the 5M160ZM100I5N excels as a reconfigurable bridge. Its 7.5 ns pin-to-pin delay enables tight bus-cycle timing, while the flash-backed configuration means no external boot PROM is needed. The 100-ball MBGA footprint fits on standard 4-layer PCBs with 0.8 mm pitch BGA fan-out. Engineers typically use it to convert an 8-bit parallel ADC interface to SPI, generate chip-select and write-enable strobes for legacy SRAM/Flash, or implement a custom async UART. Quartus Prime IP libraries include bus-interface functions that accelerate development. Low standby current (tens of microamps) makes it attractive for battery-backed bridging applications where the host SoC is in sleep.
Recommended
Power-Up Sequencing and Supervisory Control
Power-sequencing multiple voltage rails is one of the canonical uses for a MAX V CPLD like the 5M160ZM100I5N. Because its configuration is non-volatile, the device begins executing its logic state machine the instant VCCINT ramps above 1.8 V, well before the downstream PMIC or MCU is ready. The 128 macro cells are sufficient to implement cascaded enable signals, fault latching, and reset distribution for systems with 4-8 power rails. JTAG ISP allows board-level firmware updates via USB-Blaster or compatible programmers without removing the part. The part's industrial temperature grade supports automotive under-hood and outdoor telecom applications. Compared to a discrete supervisor IC + GPIO expander solution, a single CPLD consolidates the logic and reduces board area.
Recommended
Motor and LED Driving Logic
Stepper motors, BLDC commutation, and multi-channel LED PWM dimmers all benefit from the deterministic timing of a CPLD like the 5M160ZM100I5N. The 7.5 ns tPD lets the part generate accurate PWM edges and commutate Hall-sensor inputs without software jitter. With 79 user I/Os, the device can drive several channels of high-side/low-side FET control logic, plus interface to encoders and limit switches. Designers use Quartus Prime state-machine libraries to implement field-oriented control pre-processing or LED color-mixing algorithms. The non-volatile flash means that the controller comes up with valid commutation signals even before the main MCU firmware loads, eliminating dangerous motor-start glitches during boot.
Recommended
Low-Power Portable and Battery-Backed Designs
The 5M160ZM100I5N's standby current in the tens of microamps makes it ideal for battery-backed portable products where a small amount of always-on glue logic must persist through sleep cycles. Examples include a wake-from-sleep state machine, button-debounce and long-press detection, or RTC interrupt routing. Its instant-on behavior eliminates the wake-from-FPGA configuration delay that plagues SRAM-based FPGAs. Industrial temp grade covers outdoor and automotive portable applications. The 1.8 V core is friendly to single-cell Li-ion or coin-cell regulator outputs, simplifying the power tree. Designers can use Quartus Prime low-power synthesis options to further minimize dynamic current at low toggle rates.
Recommended
Legacy Interface Adaptation
Many modern SoCs and FPGAs have dropped legacy interfaces (VGA, parallel RGB LCD, ISA bus, PS/2, parallel NOR flash) but industrial and medical products still need them. The 5M160ZM100I5N is a cost-effective adapter: feed it a modern LVDS or RGB output and reconstruct legacy timing, or vice versa. With 128 macro cells, complex state machines for VGA pixel clocks, PS/2 bit-banging, or LCD timing generation fit comfortably. The non-volatile flash configuration survives power cycles without reconfiguration delay. Multi-voltage I/O banks let it directly interface to 5 V-tolerant legacy devices through appropriate resistor dividers or level shifters. Quartus Prime synthesis supports legacy timing constraints critical for accurate pixel-clock generation.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZM100I5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZM100C5N | 5M160ZM100C4N | 5M160ZM100A5N | 5M160ZE64I5N | 5M1270ZT144I5N |
|---|---|---|---|---|---|---|
| Package | 100-ball MBGA | 100-ball MBGA (same) | 100-ball MBGA (same) | 100-ball MBGA (same) | EQFP-64 | TQFP-144 |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macro Cells / Logic Elements | 128 macro cells | 128 macro cells | 128 macro cells | 128 macro cells | 64 macro cells | 1270 LE |
| User I/Os | 79 | 79 | 79 | 79 | 30-40 (EQFP-64) | 112 (TQFP-144) |
| Pin-to-Pin Delay (tPD) | 7.5 ns (I5 speed grade) | 7.5 ns | 9.0 ns (C4 slower) | 7.5 ns | 7.5 ns | 6.0 ns |
| Internal fMAX | 118.3 MHz at 1.8 V | 118.3 MHz | ~100 MHz | 118.3 MHz | 118.3 MHz | 152 MHz |
| Temperature Grade | Industrial -40C to +100C | Commercial 0C to +85C | Commercial 0C to +85C | Automotive -40C to +125C | Industrial -40C to +100C | Industrial -40C to +100C |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Approx. Unit Price (qty 100) | $9.85 USD | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Industrial temperature grade in same pinout (vs 5M160ZM100C5N)
- Fastest speed grade in the 100-ball MBGA family (vs 5M160ZM100C4N)
- Non-volatile flash configuration eliminates boot PROM (vs SRAM-based FPGAs (e.g., Cyclone V))
Design Notes
Decouple VCCINT (1.8 V core) and each VCCIO bank (1.5/1.8/2.5/3.3 V) with a 0.1 uF ceramic capacitor placed within 3 mm of each supply ball, plus a bulk 10 uF tantalum or polymer capacitor near the package. Each I/O bank must be powered before any signal is applied to its I/O pins to prevent latch-up; unused banks should still be tied to a valid voltage rather than left floating. Estimated: with 79 I/Os at 10 MHz toggle and 5 pF load, dynamic current is roughly 10 mA, dominated by the core static current of a few hundred microamps.
The 100-ball MBGA package has a 0.8 mm ball pitch and requires 4-layer PCB with microvia-in-pad or via-in-pad plating for reliable assembly. Fan-out routing should keep escape traces short and use a dog-bone or via-in-pad pattern. Matched-length routing is not critical for general logic at <100 MHz, but keep JTAG trace lengths under 50 mm and series-terminate TCK with 33 ohm if the cable exceeds 100 mm. Provide a keep-out zone under the BGA for rework accessibility.
Do not confuse MAX V speed grade suffix 'I5' (industrial temp, fastest) with 'C5' (commercial, same speed) or 'C4' (commercial, slower). Also avoid applying 5 V signals directly to any I/O bank - the absolute maximum is VCCIO + 0.3 V. When migrating designs between 5M160Z, 5M1270Z, and 5M2210Z in the same package footprint, confirm the Quartus fitter report, as larger devices may consume more I/O banks for internal logic and reduce the user-available pin count.
Compliance Information
RoHS and REACH compliant per Intel product page. AEC-Q100 qualification is not formally declared; the A5N speed/temperature variant is intended for automotive use but should be verified against the latest Intel PCN for full Q100 status.
