5M160ZM100A5N - MAX V CPLD, 128 Macrocells, 100-FBGA | Intel
MPN: 5M160ZM100A5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.8 | $7.80 |
| 10 | $7.02 | $70.20 |
| 100 | $6.24 | $624.00 |
| 500 | $5.61 | $2,805.00 |
| 1,000 | $5 | $5,000.00 |
Drop-in alternatives for 5M160ZM100A5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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5M160ZM100I5N
β Drop-Inβ In Stock
$7.1 / Unit
View Datasheet β5M240ZM100I5N
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$9.85 / Unit
View Datasheet β5M160ZM100A5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Logic Elements / Macrocells | 128 macrocells |
| Maximum User I/Os | 79 |
| Operating Frequency (fMAX) | 118.3 MHz |
| Propagation Delay (tPD) | 14 ns (industrial, A5 speed grade) |
| Core Supply Voltage (VCCINT) | 1.8 V (internal) |
| I/O Supply Voltage (VCCIO) | 1.2 V to 3.3 V |
| User Flash Memory | 8 Kbits |
| Programming Interface | JTAG (IEEE 1532 / IEEE 1149.1) |
| Standby Current (ICCSTBY) | 25 Β΅A typical |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial) |
| Package | 100-ball Micro FBGA (M100) 6x6 mm, 0.5 mm pitch |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
5M160ZM100A5N Pin Configuration
| Pin A1 | I/O β User I/O pin (bank 1) |
| Pin A2 | I/O β User I/O pin (bank 1) |
| Pin A3 | I/O β User I/O pin (bank 1) |
| Pin A4 | I/O β User I/O pin (bank 1) |
| Pin A5 | I/O β User I/O pin (bank 1) |
| Pin A6 | I/O β User I/O pin (bank 1) |
| Pin A7 | I/O β User I/O pin (bank 1) |
| Pin A8 | I/O β User I/O pin (bank 1) |
| Pin A9 | I/O β User I/O pin (bank 1) |
| Pin A10 | I/O β User I/O pin (bank 1) |
| Pin B1 | GND β Ground |
| Pin B2 | I/O β User I/O pin (bank 2) |
| Pin B3 | I/O β User I/O pin (bank 2) |
| Pin B4 | I/O β User I/O pin (bank 2) |
| Pin B5 | I/O β User I/O pin (bank 2) |
| Pin B6 | I/O β User I/O pin (bank 2) |
| Pin B7 | I/O β User I/O pin (bank 2) |
| Pin B8 | I/O β User I/O pin (bank 2) |
| Pin B9 | I/O β User I/O pin (bank 2) |
| Pin B10 | VCCIO1 β I/O supply voltage bank 1 |
| Pin C1 | I/O β User I/O pin (bank 3) |
| Pin C2 | I/O β User I/O pin (bank 3) |
| Pin C3 | I/O β User I/O pin (bank 3) |
| Pin C4 | I/O β User I/O pin (bank 3) |
| Pin C5 | GND β Ground |
| Pin C6 | I/O β User I/O pin (bank 3) |
| Pin C7 | I/O β User I/O pin (bank 3) |
| Pin C8 | I/O β User I/O pin (bank 3) |
| Pin C9 | I/O β User I/O pin (bank 3) |
| Pin C10 | VCCIO2 β I/O supply voltage bank 2 |
| Pin D1 | I/O β User I/O pin (bank 4) |
| Pin D2 | I/O β User I/O pin (bank 4) |
| Pin D3 | I/O β User I/O pin (bank 4) |
| Pin D4 | TDI β JTAG Test Data In |
| Pin D5 | TMS β JTAG Test Mode Select |
| Pin D6 | TCK β JTAG Test Clock |
| Pin D7 | TDO β JTAG Test Data Out |
| Pin D8 | I/O β User I/O pin (bank 4) |
| Pin D9 | I/O β User I/O pin (bank 4) |
| Pin D10 | VCCIO3 β I/O supply voltage bank 3 |
| Pin E1 | I/O β User I/O pin (bank 5) |
| Pin E2 | I/O β User I/O pin (bank 5) |
| Pin E3 | I/O β User I/O pin (bank 5) |
| Pin E4 | I/O β User I/O pin (bank 5) |
| Pin E5 | GND β Ground |
| Pin E6 | I/O β User I/O pin (bank 5) |
| Pin E7 | I/O β User I/O pin (bank 5) |
| Pin E8 | I/O β User I/O pin (bank 5) |
| Pin E9 | I/O β User I/O pin (bank 5) |
| Pin E10 | VCCIO4 β I/O supply voltage bank 4 |
| Pin F1 | I/O β User I/O pin (bank 6) |
| Pin F2 | I/O β User I/O pin (bank 6) |
| Pin F3 | I/O β User I/O pin (bank 6) |
| Pin F4 | I/O β User I/O pin (bank 6) |
| Pin F5 | VCCINT β Core supply voltage (1.8 V internal) |
| Pin F6 | I/O β User I/O pin (bank 6) |
| Pin F7 | I/O β User I/O pin (bank 6) |
| Pin F8 | I/O β User I/O pin (bank 6) |
| Pin F9 | I/O β User I/O pin (bank 6) |
| Pin F10 | VCCIO5 β I/O supply voltage bank 5 |
| Pin G1 | I/O β User I/O pin (bank 7) |
| Pin G2 | I/O β User I/O pin (bank 7) |
| Pin G3 | I/O β User I/O pin (bank 7) |
| Pin G4 | I/O β User I/O pin (bank 7) |
| Pin G5 | GND β Ground |
| Pin G6 | I/O β User I/O pin (bank 7) |
| Pin G7 | I/O β User I/O pin (bank 7) |
| Pin G8 | I/O β User I/O pin (bank 7) |
| Pin G9 | I/O β User I/O pin (bank 7) |
| Pin G10 | VCCIO6 β I/O supply voltage bank 6 |
| Pin H1 | I/O β User I/O pin (bank 8) |
| Pin H2 | I/O β User I/O pin (bank 8) |
| Pin H3 | I/O β User I/O pin (bank 8) |
| Pin H4 | I/O β User I/O pin (bank 8) |
| Pin H5 | nCONFIG β Configuration start input (active low) |
| Pin H6 | nSTATUS β Configuration status output (active low) |
| Pin H7 | CONF_DONE β Configuration done output |
| Pin H8 | I/O β User I/O pin (bank 8) |
| Pin H9 | I/O β User I/O pin (bank 8) |
| Pin H10 | VCCIO7 β I/O supply voltage bank 7 |
| Pin J1 | I/O β User I/O pin (bank 8) |
| Pin J2 | I/O β User I/O pin (bank 8) |
| Pin J3 | I/O β User I/O pin (bank 8) |
| Pin J4 | I/O β User I/O pin (bank 8) |
| Pin J5 | I/O β User I/O pin (bank 8) |
| Pin J6 | I/O β User I/O pin (bank 8) |
| Pin J7 | I/O β User I/O pin (bank 8) |
| Pin J8 | I/O β User I/O pin (bank 8) |
| Pin J9 | I/O β User I/O pin (bank 8) |
| Pin J10 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZM100A5N is suitable for 6 applications: Industrial PLC I/O Expansion and Level Translation, FPGA/SoC Power Sequencing Controller, Bus Bridging Between Legacy MCU and Modern Processor, Glue Logic for Telecom Baseband Boards, Automotive-Grade I/O Expansion (Non-Safety Domain), Test and Measurement Equipment Front-End Logic.
Industrial PLC I/O Expansion and Level Translation
The 5M160ZM100A5N is well matched to industrial PLC I/O expansion because its 79 user I/Os and MultiVolt bank architecture (1.2 V to 3.3 V) allow direct interfacing between 1.8 V microcontroller buses and 3.3 V or 5 V-tolerant field-side peripherals without external level shifters. The 128 macrocells comfortably accommodate 8-bit to 16-bit address decoding, interrupt steering, and timing-critical control registers typical of PLC backplane logic. The 25 Β΅A typical standby current supports always-on industrial nodes where energy budget is tight. The instant-on non-volatile flash configuration ensures deterministic startup, a regulatory requirement in many safety-rated PLCs. Per the MAX V datasheet, the industrial -40 Β°C to +85 Β°C operating range covers the majority of factory-floor enclosures without derating. For companion parts, the 5M1270 series offers similar functionality in larger packages, while discrete logic gates can offload simple functions.
Recommended
FPGA/SoC Power Sequencing Controller
The 5M160ZM100A5N serves as a dedicated power-sequencing controller for FPGA and SoC rails because its instant-on flash-based configuration provides deterministic enable-signal timing at power-up, eliminating the configuration latency of SRAM-based FPGAs. Per the MAX V datasheet, the device can generate multiple sequenced enable pulses with 14 ns tPD resolution, suiting multi-rail power trees for processors requiring specific startup order (e.g., core before I/O before analog). The 1.8 V core and 3.3 V-tolerant I/O banks interface directly to common DC-DC enable inputs and PG (power-good) signals from regulators like the LTM4675 or TPS54A20. The 25 Β΅A standby current keeps quiescent draw negligible in battery-backed sequencing paths.
Recommended
Bus Bridging Between Legacy MCU and Modern Processor
The 5M160ZM100A5N is ideal for bus bridging between legacy microcontrollers and modern SoCs because its 128 macrocells can implement 8-bit/16-bit to 32-bit width conversion, protocol translation, and wait-state insertion logic in a single non-volatile device. Per the MAX V datasheet, the 118.3 MHz fMAX comfortably handles UART-to-SPI bridges, parallel memory-mapped interfaces, and interrupt aggregation at typical MCU bus speeds. The MultiVolt I/O eliminates external level shifters when bridging between 1.8 V ARM cores and 3.3 V legacy 8051 peripherals, reducing BOM and PCB complexity. The industrial temperature rating suits embedded modules in outdoor telecom and industrial cabinets.
Recommended
Glue Logic for Telecom Baseband Boards
The 5M160ZM100A5N integrates discrete glue logic on telecom baseband boards because its non-volatile flash configuration and 25 Β΅A standby current reduce board-level power consumption and BOM cost compared to implementing the same logic with multiple 74-series gates. Per the MAX V datasheet, the 14 ns tPD supports timing-critical chip-select generation for DDR memory controllers, interrupt prioritization for baseband DSPs, and reset-distribution networks for multi-chip baseband subsystems. The 100-ball Micro FBGA package provides high pin density for compact baseband mezzanine cards where board area is at a premium. JTAG-based in-system programmability simplifies field firmware updates without removing the baseband module.
Recommended
Automotive-Grade I/O Expansion (Non-Safety Domain)
The 5M160ZM100A5N serves in non-safety automotive I/O expansion roles such as body-control modules and infotainment sub-systems because its industrial -40 Β°C to +85 Β°C temperature range covers most cabin environments, and its non-volatile flash configuration eliminates boot-time latency during cold-crank events. Per the MAX V datasheet, the 79 user I/Os support LIN/CAN auxiliary bus decoding, LED matrix driving, and HVAC control-panel scanning. The MultiVolt I/O banks allow direct connection to 3.3 V body-control MCUs and 5 V analog sensor front-ends. The device is not AEC-Q100 qualified; for safety-domain applications choose the AEC-Q100-grade MAX V variants or alternative CPLD families explicitly qualified to that standard.
Recommended
Test and Measurement Equipment Front-End Logic
The 5M160ZM100A5N provides deterministic front-end logic for test and measurement equipment because its 14 ns tPD and 118.3 MHz fMAX enable precise timing of multiplexers, range-switching networks, and trigger-conditioning circuits in oscilloscopes and data-acquisition front-ends. Per the MAX V datasheet, the 128 macrocells implement complex trigger state machines that would otherwise require discrete programmable timers. The instant-on configuration supports rapid instrument power-up without user-visible boot delay. The 100-ball Micro FBGA package footprint suits compact handheld instrument designs where PCB real estate is constrained and thermal management favors low-power non-volatile logic.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZM100A5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZM100I5N | 5M240ZM100I5N |
|---|---|---|---|
| Package | 100-ball Micro FBGA (M100) | 100-ball Micro FBGA (M100) - same | 100-ball Micro FBGA (M100) - same |
| Brand | Intel (formerly Altera) | Intel | Intel |
| Macrocells | 128 | 128 (same) | 240 (+88%) |
| Maximum User I/Os | 79 | 79 (same) | 79 (same) |
| Speed Grade | A5 (industrial) | I5 (faster, industrial) | I5 (faster, industrial) |
| Operating Frequency (fMAX) | 118.3 MHz | [DATA_NEEDED] | [DATA_NEEDED] |
| Propagation Delay (tPD) | 14 ns | [DATA_NEEDED] | [DATA_NEEDED] |
| User Flash Memory | 8 Kbits | 8 Kbits (same) | 8 Kbits (same) |
| Standby Current | 25 Β΅A typical | 25 Β΅A typical (same) | [DATA_NEEDED] |
| Pin-to-Pin Drop-In | Yes (this MPN) | Yes (same M100 footprint) | Yes (same M100 footprint) |
Key Differentiators
- Non-volatile flash configuration with instant-on behavior (vs 5M160ZM100I5N)
- Direct drop-in upgrade path to 240 macrocells in same package (vs 5M240ZM100I5N)
- MultiVolt I/O banks (1.2 V to 3.3 V) eliminate external level shifters (vs 5CEBA2F17I7N (Cyclone V FPGA))
Design Notes
The 5M160ZM100A5N requires a stable 1.8 V VCCINT and one or more VCCIO bank supplies between 1.2 V and 3.3 V. Decouple each VCCIO bank with a 0.1 Β΅F ceramic capacitor placed within 3 mm of the package ball, plus a bulk 10 Β΅F tantalum or ceramic capacitor near the supply entry point. Per the MAX V datasheet, VCCINT is internally regulated from the VCC supply on most variants, but the 1.8 V rail must still be decoupled to suppress switching noise. Avoid routing high-speed signals across the VCCINT balls to prevent supply-noise coupling into logic macros.
The 100-ball Micro FBGA (M100) package uses a 0.5 mm ball pitch requiring microvia or fine-pitch PCB technology (4-layer minimum recommended). Use a via-in-pad or dog-bone fanout pattern with 0.2 mm / 0.4 mm capture pad dimensions per the MAX V hardware design guidelines. Per the MAX V datasheet, keep all signal traces at least 0.2 mm away from the edge of the BGA land pads to avoid solder bridging. The exposed die-attach paddle on the package underside must be soldered to the PCB ground plane for thermal dissipation and electrical return.
Do not leave the JTAG TDI, TMS, TCK, or TDO balls floating during normal operation; tie TMS and TDI high through 10 kΞ© pull-ups to VCCIO of the configuration bank, per the MAX V datasheet. Floating JTAG inputs can cause spurious configuration attempts. The nCONFIG input is active-low and must return high after a valid reset pulse width; ensure the reset RC time constant is at least 1 Β΅s. Do not apply power to VCCIO before VCCINT - the I/O drivers may back-power the core through ESD protection diodes. Sequence supplies such that VCCINT (or its internal regulator input) rises before VCCIO.
For 118.3 MHz fMAX designs, controlled-impedance routing (50 Ξ© single-ended) is required on all clock and high-speed I/O traces longer than approximately 10 mm. Per the MAX V datasheet, the I/O driver slew-rate and strength settings should be adjusted in the Quartus II / Quartus Prime pin planner to optimize signal integrity for each bank; default settings are conservative. Use series termination resistors on clock outputs driving multiple loads. Ground bounce can be minimized by distributing VCCIO and GND balls evenly across switching I/O banks.
Compliance Information
RoHS compliant and lead-free per Intel product page. Not AEC-Q100 qualified - industrial temperature grade (-40 Β°C to +85 Β°C) only. Choose AEC-Q100-qualified MAX V or alternative CPLD families for safety-domain automotive applications.
