5M80ZT100I5N - MAX V 80LE CPLD 7.5ns TQFP-100 | Intel
MPN: 5M80ZT100I5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.1 | $111.00 |
| 100 | $9.4 | $940.00 |
| 500 | $8.2 | $4,100.00 |
| 1,000 | $7.3749 | $7,374.90 |
Drop-in alternatives for 5M80ZT100I5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M40ZT100I5N
β Drop-Inπ Reference alternative (not in catalog)
5M160ZT100I5N
β Drop-Inβ In Stock
$4.1 / Unit
View Datasheet β5M240ZT100I5N
β Drop-Inβ In Stock
$4.81 / Unit
View Datasheet β5M570ZT100I5N
β Drop-Inβ In Stock
$6.74 / Unit
View Datasheet β5M80ZT100C5N
β Drop-Inβ In Stock
$4.1 / Unit
View Datasheet β5M80ZT100A5N
β Drop-Inβ In Stock
$1.85 / Unit
View Datasheet β5M80ZT100I5N Maximum Ratings & Electrical Characteristics
| Family | MAX V CPLD |
| Logic Elements (LE) | 80 |
| Macrocells (approx.) | 160 |
| User I/O Pins | 64 |
| Package | TQFP-100 (100 pins, 0.5 mm pitch) |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V typical) |
| I/O Supply Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature (Industrial) | -40 Β°C to +100 Β°C |
| Configuration Memory | Internal non-volatile flash (instant-on) |
| UFM (User Flash Memory) | Up to 8 Kbits user-accessible |
| JTAG / ISP | IEEE 1149.1 boundary-scan + in-system programming |
| Mounting Type | Surface Mount |
| MSL Level | MSL3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
5M80ZT100I5N Pin Configuration
| Pin 1 | I/O β General purpose I/O - Bank 1 |
| Pin 2 | I/O β General purpose I/O - Bank 1 |
| Pin 3 | I/O β General purpose I/O - Bank 1 |
| Pin 4 | I/O β General purpose I/O - Bank 1 |
| Pin 5 | I/O β General purpose I/O - Bank 1 |
| Pin 6 | I/O β General purpose I/O - Bank 1 |
| Pin 7 | I/O β General purpose I/O - Bank 1 |
| Pin 8 | I/O β General purpose I/O - Bank 1 |
| Pin 9 | I/O β General purpose I/O - Bank 1 |
| Pin 10 | I/O β General purpose I/O - Bank 1 |
| Pin 11 | I/O β General purpose I/O - Bank 1 |
| Pin 12 | I/O β General purpose I/O - Bank 1 |
| Pin 13 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 14 | I/O β General purpose I/O - Bank 1 |
| Pin 15 | I/O β General purpose I/O - Bank 1 |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β General purpose I/O - Bank 1 |
| Pin 18 | I/O β General purpose I/O - Bank 1 |
| Pin 19 | I/O β General purpose I/O - Bank 1 |
| Pin 20 | I/O β General purpose I/O - Bank 1 |
| Pin 21 | I/O β General purpose I/O - Bank 1 |
| Pin 22 | I/O β General purpose I/O - Bank 1 |
| Pin 23 | I/O β General purpose I/O - Bank 1 |
| Pin 24 | I/O β General purpose I/O - Bank 1 |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β General purpose I/O - Bank 2 |
| Pin 27 | I/O β General purpose I/O - Bank 2 |
| Pin 28 | I/O β General purpose I/O - Bank 2 |
| Pin 29 | I/O β General purpose I/O - Bank 2 |
| Pin 30 | I/O β General purpose I/O - Bank 2 |
| Pin 31 | I/O β General purpose I/O - Bank 2 |
| Pin 32 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 33 | I/O β General purpose I/O - Bank 2 |
| Pin 34 | I/O β General purpose I/O - Bank 2 |
| Pin 35 | I/O β General purpose I/O - Bank 2 |
| Pin 36 | I/O β General purpose I/O - Bank 2 |
| Pin 37 | I/O β General purpose I/O - Bank 2 |
| Pin 38 | I/O β General purpose I/O - Bank 2 |
| Pin 39 | I/O β General purpose I/O - Bank 2 |
| Pin 40 | I/O β General purpose I/O - Bank 2 |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β General purpose I/O - Bank 2 |
| Pin 43 | I/O β General purpose I/O - Bank 2 |
| Pin 44 | I/O β General purpose I/O - Bank 2 |
| Pin 45 | I/O β General purpose I/O - Bank 2 |
| Pin 46 | I/O β General purpose I/O - Bank 2 |
| Pin 47 | I/O β General purpose I/O - Bank 2 |
| Pin 48 | I/O β General purpose I/O - Bank 2 |
| Pin 49 | VCCINT β Core supply voltage (1.8 V) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β General purpose I/O - Bank 3 |
| Pin 52 | I/O β General purpose I/O - Bank 3 |
| Pin 53 | I/O β General purpose I/O - Bank 3 |
| Pin 54 | I/O β General purpose I/O - Bank 3 |
| Pin 55 | I/O β General purpose I/O - Bank 3 |
| Pin 56 | I/O β General purpose I/O - Bank 3 |
| Pin 57 | I/O β General purpose I/O - Bank 3 |
| Pin 58 | I/O β General purpose I/O - Bank 3 |
| Pin 59 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 60 | I/O β General purpose I/O - Bank 3 |
| Pin 61 | I/O β General purpose I/O - Bank 3 |
| Pin 62 | I/O β General purpose I/O - Bank 3 |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β General purpose I/O - Bank 3 |
| Pin 65 | I/O β General purpose I/O - Bank 3 |
| Pin 66 | I/O β General purpose I/O - Bank 3 |
| Pin 67 | I/O β General purpose I/O - Bank 3 |
| Pin 68 | I/O β General purpose I/O - Bank 3 |
| Pin 69 | I/O β General purpose I/O - Bank 3 |
| Pin 70 | I/O β General purpose I/O - Bank 3 |
| Pin 71 | I/O β General purpose I/O - Bank 3 |
| Pin 72 | I/O β General purpose I/O - Bank 3 |
| Pin 73 | I/O β General purpose I/O - Bank 3 |
| Pin 74 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 75 | I/O β General purpose I/O - Bank 3 |
| Pin 76 | GND β Ground |
| Pin 77 | I/O β General purpose I/O - Bank 4 |
| Pin 78 | I/O β General purpose I/O - Bank 4 |
| Pin 79 | I/O β General purpose I/O - Bank 4 |
| Pin 80 | I/O β General purpose I/O - Bank 4 |
| Pin 81 | I/O β General purpose I/O - Bank 4 |
| Pin 82 | VCCIO4 β Bank 4 I/O supply voltage |
| Pin 83 | I/O β General purpose I/O - Bank 4 |
| Pin 84 | I/O β General purpose I/O - Bank 4 |
| Pin 85 | TDI β JTAG test data input (IEEE 1149.1) |
| Pin 86 | TMS β JTAG test mode select |
| Pin 87 | TCK β JTAG test clock |
| Pin 88 | TDO β JTAG test data output |
| Pin 89 | GND β Ground |
| Pin 90 | nSTATUS β Configuration status (open-drain) |
| Pin 91 | CONF_DONE β Configuration done indicator |
| Pin 92 | nCONFIG β Configuration start (active-low) |
| Pin 93 | I/O β General purpose I/O - Bank 4 |
| Pin 94 | I/O β General purpose I/O - Bank 4 |
| Pin 95 | I/O β General purpose I/O - Bank 4 |
| Pin 96 | I/O β General purpose I/O - Bank 4 |
| Pin 97 | I/O β General purpose I/O - Bank 4 |
| Pin 98 | I/O β General purpose I/O - Bank 4 |
| Pin 99 | I/O β General purpose I/O - Bank 4 |
| Pin 100 | I/O β General purpose I/O - Bank 4 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZT100I5N is suitable for 6 applications: MCU I/O Expansion and Voltage Translation, Power-Sequencing and Reset Control, Industrial Control and Factory Automation, Bus Address Decoding and Memory Interfacing, Board-Level Glue Logic Replacement, Automotive Cabin Electronics.
MCU I/O Expansion and Voltage Translation
The 5M80ZT100I5N is frequently used to expand a microcontroller's limited GPIO count and to translate between mismatched voltage domains. With 64 user I/O across four MultiVolt banks supporting 1.2 V/1.5 V/1.8 V/2.5 V/3.3 V, it can sit between a 3.3 V MCU and a 1.8 V sensor array without external level shifters. The 80 Logic Elements handle simple address decoding, mux/select logic, and PWM fan-out, while the 7.5 ns tPD supports typical peripheral buses (SPI, I2C, UART) without timing bottlenecks.
Recommended
Power-Sequencing and Reset Control
The 5M80ZT100I5N's instant-on flash architecture (sub-100 Β΅s wake-up) makes it ideal for multi-rail power-sequencing controllers in networking switches, servers, and FPGA-based SoCs. The 80 LE implement cascaded timer chains for staggered rail enable, monitor PG (power-good) inputs, and drive external MOSFET gates. Its industrial -40 Β°C to +100 Β°C range ensures reliable cold-start sequencing at -40 Β°C, and the MultiVolt I/O can directly interface with PMBus controllers and eFuses on 1.8 V or 3.3 V rails.
Recommended
Industrial Control and Factory Automation
The 5M80ZT100I5N's industrial temperature grade (-40 Β°C to +100 Β°C) and deterministic timing make it well suited to PLC digital I/O cards, motor-control front-ends, and sensor-conditioning boards. Its 64 I/O handle 24 V optically-isolated inputs via external resistor networks, encode quadrature signals, or drive relay coils. The instant-on non-volatile configuration survives brown-outs and factory floor EMI events without boot failures, while the 7.5 ns tPD implements deterministic state-machine responses in safety-critical loops.
Recommended
Bus Address Decoding and Memory Interfacing
Address decoding for memory banks and peripheral selects is a classic CPLD use case. The 5M80ZT100I5N's 7.5 ns tPD can decode a 16-bit address in well under one memory cycle, while 80 LE easily handle 8-to-16 chip-select outputs across multiple voltage banks. This makes it ideal for legacy designs bridging 8-bit MCUs to 16/32-bit memory buses, or for adding chip-enable logic to SRAM, NOR flash, and FRAM arrays without using precious MCU GPIO. Source: Intel MAX V design handbook typical-application section.
Recommended
Board-Level Glue Logic Replacement
The 5M80ZT100I5N replaces multiple discrete 74HC/74AHC packages - gates, latches, muxes, decoders, monostables - consolidating them into a single re-programmable device. This shrinks BOM count, reduces PCB area, simplifies inventory, and adds design flexibility for late-stage changes. The 80 LE and 64 I/O are sufficient to replace 10-20 discrete logic packages in a typical interface board, while the industrial temperature grade supports harsh-environment deployments. Source: Intel MAX V application note AN-428.
Recommended
Automotive Cabin Electronics
Within cabin (non-ADAS) automotive modules such as HVAC controllers, body-control modules, infotainment interfaces, and instrument clusters, the 5M80ZT100I5N provides deterministic GPIO expansion and voltage translation. The 'I5N' industrial grade operates to +100 Β°C, sufficient for cabin environments; for under-hood or AEC-Q100 qualified applications, the 'A5N' automotive variant or a higher-grade MAX V device is recommended. Its instant-on behavior avoids cold-start races with the host MCU, and JTAG ISP enables end-of-line programming.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZT100I5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M40ZT100I5N | 5M160ZT100I5N | 5M240ZT100I5N | 5M570ZT100I5N | 5M80ZT100C5N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Logic Elements | 80 | 40 (-50%) | 160 (+100%) | 240 (+200%) | 570 (+612%) | 80 (same) |
| User I/O Pins | 64 | 64 (same) | 64 (same) | 64 (same) | 64 (same) | 64 (same) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns | 7.5 ns | 7.5 ns | 9.0 ns | 7.5 ns |
| Core Voltage (VCCINT) | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V |
| Operating Temperature | -40C to +100C (Industrial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) | 0C to +85C (Commercial) |
| Configuration Memory | Internal flash (non-volatile) | Internal flash (non-volatile) | Internal flash (non-volatile) | Internal flash (non-volatile) | Internal flash (non-volatile) | Internal flash (non-volatile) |
| Approx. Unit Price (USD, qty 1000) | 7.37 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Instant-on non-volatile flash eliminates boot PROM (vs Small SRAM FPGAs (Cyclone IV, Spartan-6))
- MultiVolt I/O banks natively bridge 1.2 V to 3.3 V (vs Discrete 74LVC/74AVC level shifters)
- Pin-compatible density scaling within MAX V family (vs 5M40ZT100I5N and 5M160ZT100I5N)
Design Notes
Decouple every VCCINT and VCCIO pin with a 0.1 microfarad ceramic capacitor placed within 50 mil of the package pin; add a 1 microfarat bulk capacitor near each VCCIO bank. Estimated: assuming 80 LE switching at 50 MHz with typical toggle rates, the 1.8 V core draws roughly 15-25 mA active and under 50 microamp standby - place one 10 microfarat tantalum near the VCCINT rail to handle inrush during instant-on. Source: Intel MAX V power estimation spreadsheet.
The TQFP-100 package has a thermal pad area of approximately 8 mm x 8 mm. While the MAX V family is low-power (under 100 mW typical), a continuous ground pour on all four layers directly under the package improves thermal performance and reduces ground bounce. Keep high-speed traces (clock, JTAG) on inner layers to minimize EMI. Source: Intel MAX V hardware design guide.
Do not mix 3.3 V and 1.5 V signaling on the same VCCIO bank - each bank shares a single VCCIO supply rail, so mixed-voltage groups must be assigned to separate banks (1-4). Failing to observe this constraint causes input leakage or logic errors. Also, the JTAG pins (TDI/TMS/TCK/TDO) must be pulled to a defined state during normal operation; a floating TCK can latch the TAP controller into a test mode. Source: Intel MAX V device handbook.
Compliance Information
RoHS compliant per Intel product page. The 5M80ZT100I5N itself is industrial-grade (I5N), not AEC-Q100 qualified; for automotive applications use 5M80ZT100A5N (if available) or a dedicated AEC-Q100 qualified CPLD.
