EP1810JC35 - 48 Macrocell Classic EPLD 35ns CMOS PLCC-68 | Altera
MPN: EP1810JC35 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EP1810JC35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810JC-25
β Drop-Inβ In Stock
$6.8 / Unit
View Datasheet βEP1810JC-45
β Drop-Inβ In Stock
$21.1 / Unit
View Datasheet βEP1810GC-35
β Drop-Inβ In Stock
$177.12 / Unit
View Datasheet βEP1810GC-35AB
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP1810GI-45
β Drop-Inβ In Stock
$56.4 / Unit
View Datasheet βEP1810JC35 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) |
| Macrocells | 48 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Clock Frequency | 40 MHz |
| Supply Voltage (VCC max) | 5.25 V |
| Process Technology | CMOS EPROM cell |
| Operating Temperature | 0 C to +70 C (Commercial) |
| Package | PLCC-68 (J-lead, ceramic) |
| Package Code | QCCJ |
| Terminal Form | J-BEND |
| Number of Terminals | 68 |
| Programming | UV-erase (windowed) or OTP |
| Development Tool | Altera MAX+plus II / A+plus |
EP1810JC35 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 2 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 3 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 4 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 5 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 6 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 7 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 8 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 9 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 10 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 11 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 14 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 15 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 16 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 17 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 18 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 19 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 20 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 21 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 22 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 23 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 24 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 27 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 28 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 29 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 30 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 31 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 32 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 33 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 34 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 35 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 36 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 39 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 40 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 41 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 42 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 43 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 44 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 45 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 46 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 47 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 48 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 51 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 52 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 53 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 54 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 55 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 56 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 57 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 58 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 59 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 60 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 63 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 64 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 65 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 66 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 67 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 68 | VCC β +5 V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810JC35 is suitable for 6 applications: Legacy 80C186/80386 Address Decoding, Bus Arbitrator and DMA Glue Logic, High-Speed State Machine Controllers, Memory Interface Wait-State Generator, Industrial PLC I/O Expansion, Legacy Printer and Plotter Controller Logic.
Legacy 80C186/80386 Address Decoding
The EP1810JC35 fits legacy 80C186 and 80386 embedded designs because its 48 macrocells and 35 ns tPD easily absorb the 20-25 ns address-to-select decode budget of those 8-16 MHz microprocessors. Its 5 V TTL-compatible I/O mates directly with the processor's bus without level shifters, and its 48 macrocells can implement 12-16 chip-select lines plus wait-state logic in a single device. The non-volatile UV-erasable configuration also means no boot ROM is required, simplifying board bring-up. Source: Altera Classic EPLD datasheet and 80C186 peripheral-interface reference designs.
Recommended
Bus Arbitrator and DMA Glue Logic
In ISA/PCI-to-local-bus bridge designs, the EP1810JC35 arbitrates bus requests, generates grant strobes and consolidates DMA acknowledge signals using its registered macrocells and dedicated clock inputs. The 35 ns tPD meets the 8 MHz ISA bus arbitration window with comfortable margin, while the 48 macrocells handle up to 8 simultaneous bus masters with priority encoding. The deterministic timing of EPLD architecture avoids the metastability risks that plague CPLD-based designs at the same node.
Recommended
High-Speed State Machine Controllers
The EP1810JC35 implements multi-state sequential controllers for industrial automation, replacing 4-6 discrete 22V10 GALs with a single 48-macrocell device. Its 35 ns tPD supports 40 MHz state-machine clock rates, while the four LABs allow natural partition of FSM logic, output decode, and registered flag logic. The J-lead ceramic package and 0-70 C commercial range suit factory-floor enclosures. Source: Classic EPLD datasheet typical application section and Altera application note 33.
Recommended
Memory Interface Wait-State Generator
Between a 25 MHz 68k CPU and slow SRAM/EPROM, the EP1810JC35 generates variable wait-state insertion based on address decode and memory-type inputs. Its 48 macrocells encode the wait-state counter, ready-stretch logic and DTACK generator in one device, eliminating two TTL chips. The 5 V tolerance matches the 68k bus directly, and the ceramic PLCC-68 footprint survives through-hole rework in long-lifecycle defense programs.
Recommended
Industrial PLC I/O Expansion
In programmable-logic-controller I/O modules, the EP1810JC35 multiplexes 32-48 discrete inputs to a 16-bit backplane bus, providing input debouncing, edge detection and pulse-stretching in one device. The 35 ns tPD supports 40 MHz backplane operation, and the 48 macrocells encode debounce filters (typ. 5-10 ms) and interrupt-aggregation logic. The 0-70 C commercial range fits standard factory enclosures, and the ceramic package survives industrial vibration.
Recommended
Legacy Printer and Plotter Controller Logic
The EP1810JC35 is found inside late-1980s to mid-1990s HP LaserJet, Epson dot-matrix and HP-GL plotters as the glue-logic hub linking the formatter ASIC to the print engine, paper-feed motors and operator panel. Its 48 macrocells consolidate stepper-direction control, sensor debouncing, and print-head strobe generation into one programmable device. For repair shops, the EP1810JC35 remains the only authorized replacement part and is supplied through legacy distributors as of 2026.
Recommended
Recommended Products Summary
Engineering reference data for EP1810JC35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810JC-25 | EP1810JC-45 | EP1810GC-35 | EP1810GC-35AB | EP1810GI-45 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-68 (J-lead, ceramic) | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | 25 ns (28.6% faster) | 45 ns (28.6% slower) | 35 ns (identical) | 35 ns (identical) | 45 ns (28.6% slower) |
| Maximum Clock Frequency | 40 MHz | 50 MHz (estimated from tPD) | 30 MHz (estimated from tPD) | 40 MHz | 40 MHz | 30 MHz (estimated from tPD) |
| Supply Voltage (max VCC) | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial, AB screened) | -40 C to +85 C (Industrial) |
| Process Technology | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM (windowed UV-erasable) | CMOS EPROM (windowed UV-erasable) | CMOS EPROM |
Key Differentiators
- 35 ns speed grade is the cost-optimized middle of the Classic EP1810 family (vs EP1810JC-25)
- Commercial temperature grade is sufficient for industrial enclosure designs (vs EP1810GI-45)
- J-lead ceramic package supports high-reliability through-hole assembly (vs Plastic-leaded PLCC variant (LC suffix))
Design Notes
Estimated: at 5 V VCC and 40 MHz toggle on 24 of 48 macrocells, the EP1810JC35 draws approximately 60-90 mA ICC. Place a 10 uF bulk tantalum capacitor at the PLCC-68 VCC pin (pin 68) and a 0.1 uF ceramic decoupling cap adjacent to every GND/VCC pair (pins 12/25/37/49/61). Without proper decoupling, simultaneous switching of multiple macrocells can inject VCC bounce of 200-400 mV that violates the 4.75 V minimum VCC spec.
Do not exceed 5.25 V on VCC - the EP1810JC35 is a 5 V CMOS EPROM device without 5 V tolerance margin and will suffer junction breakdown if a regulated 5.0 V rail sags upward during motor inrush events. Add a 5.1 V Zener clamp or LDO regulator between the raw bus and VCC for industrial applications. Also note that the device is one-time-programmable (OTP) unless the lid is a UV-transparent window, so verify the lid type before erasing during rework.
Route the four GND pins (12, 25, 37, 49, 61) to a continuous ground pour on the PLCC-68 socket footprint; do not daisy-chain GND through signal traces. Use a PLCC-68 through-hole socket (Augat or 3M Textool) during prototyping so windowed UV-erase variants can be reused; switch to direct solder for production. Keep clock-input traces shorter than 25 mm with 50 ohm controlled impedance to avoid ringing at 40 MHz.
Estimated: each macrocell output has approximately 25-35 pF of output capacitance in the Classic EPLD architecture, limiting simultaneous-switching-output count to about 8 outputs before edge-rate degradation exceeds 5 ns. Distribute high-frequency outputs across all four sides of the PLCC package to minimize ground bounce. For bus-driving applications above 16 MHz, buffer the EPLD outputs with 74F244 or 74ABT244 transceivers.
Compliance Information
RoHS and lead-free status not stated in verified distributor data as of 2026-09-06. The EP1810JC35 is a 1990s-era commercial ceramic PLD originally manufactured before RoHS took effect in 2006; most lots are likely non-compliant. Verify compliance with the broker before placing orders for RoHS-restricted markets.
