Altera

EP1810GI-45 - UV PLD, 50ns, 24 Macrocells, CPGA-68 | Altera

MPN: EP1810GI-45 ✗ End of Life
In Stock Ships in 1-3 business days
[DATA_NEEDED: VCC range] Vdss Ceramic Pin Grid Array with UV window Package -45 Speed
From $56.4 USD / Unit
MOQ: 1 |
Price updated: 2026-09-06
Volume Pricing
Qty Unit Price Extended
1 $88.4 $88.40
10 $78.5 $785.00
100 $70.2 $7,020.00
500 $62.85 $31,425.00
1,000 $56.4 $56,400.00
ℹ️ All prices are in USD

Drop-in alternatives for EP1810GI-45 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EP1810GC-35

✅ Drop-In ⚠️ 参数待验证
Altera
📦 CPGA-68
EPLD (Erasable Programmable Logic Device) · Altera Classic EPLD · CMOS, UV-erasable EPROM cells · CPGA-68 (Ceramic Pin Grid Array, 68-pin) · 68 · 40 ns · 64 · 48

✓ In Stock

$177.12 / Unit

View Datasheet →

EP1810GC-35AB

✅ Drop-In ⚠️ 参数待验证
Altera
📦 CPGA-68
Classic EPLD · CMOS EPROM · 48 · 1200 · 64 · 48 · 48 · 12

✓ In Stock

$9.95 / Unit

View Datasheet →

EP1810LC-35

✅ Drop-In ⚠️ 参数待验证
Rochester Electronics
📦 CPGA-68
EPLD (Erasable Programmable Logic Device) · Classic EP1810 · 48 · 900 usable / 2100 equivalent · 28.6 MHz · 35 ns (max, '-35' speed grade) · 5 V (4.75 V to 5.25 V) · CMOS, UV-erasable EPROM

✓ In Stock

$49.2 / Unit

View Datasheet →

EP1810GM-35

✅ Drop-In ⚠️ 参数待验证
📦 CPGA-68
same 68-pin ceramic PGA, same 24 macrocells; tpd 35 ns; military temperature grade variant

📋 Reference alternative (not in catalog)

EP1810GM-45

✅ Drop-In ⚠️ 参数待验证
📦 CPGA-68
same 68-pin ceramic PGA, same 24 macrocells; same 45 ns tpd; military temperature grade variant

📋 Reference alternative (not in catalog)

EP1810GI-45 Maximum Ratings & Electrical Characteristics

Device Type UV Erasable Programmable Logic Device (EPLD)
Family Altera Classic EPLD
Macrocells 24
Flip-Flops 48
Propagation Delay (tpd) 45 ns
Speed Grade -45
Technology CMOS
Package Type Ceramic Pin Grid Array with UV window
Pin Count 68
Mounting Type Through-Hole
Programmable Yes (UV-erasable, electrically programmable)
RoHS Status Non-compliant (ceramic PGA)
Lead-Free No

EP1810GI-45 ceramic pin grid array with uv window Pin Configuration Guide

Complete pinout information for EP1810GI-45 (ceramic pin grid array with uv window package) with 68 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.

ceramic pin grid array with uv window package pinout diagram for EP1810GI-45

No detailed pinout data available for EP1810GI-45.

Refer to the datasheet for full pin configuration.

Estimated pin count: 68 pins (digital package)

Safe Operating Area (SOA) & Thermal Characteristics

Safe Operating Area Chart Default safe operating area chart for EP1810GI-45 Drain-to-Source Voltage (Vds) Drain Current (Id)

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EP1810GI-45 is suitable for 6 applications: Legacy Industrial Control Logic, Microprocessor Bus Address Decode, Glue Logic Replacement for Discrete 74-Series ICs, State Machine Controllers, I/O Expansion and Bus Multiplexing, Military and Aerospace Legacy Avionics.

🏭

Legacy Industrial Control Logic

The EP1810GI-45's 24 macrocells and 45 ns propagation delay make it well suited for legacy industrial control boards where it replaces several discrete 74LS/74HC logic ICs implementing motor-control state machines and sensor-conditioning glue. The CMOS process keeps quiescent current low, and the ceramic CPGA package tolerates the wide temperature and vibration environment of factory floors. Field engineers appreciate the UV-erasable window for last-minute logic revisions without re-spinning the PCB, an important consideration for long-life industrial equipment. The Rochester Electronics franchise supply chain continues to support these legacy control designs through their authorized Altera Classic EPLD silicon stockpile.

🖥️

Microprocessor Bus Address Decode

The EP1810GI-45's 24 macrocells and 48 flip-flops are sufficient for full 24-bit address-decode logic for microprocessors such as the 8086, 68000, or Z80 in legacy embedded systems. The 45 ns tpd aligns with the address-to-chip-select timing window of these microprocessors, ensuring that peripheral enables remain glitch-free even at the rated bus-clock frequencies. CMOS technology reduces the Icc draw of address-decode PLDs versus bipolar PAL counterparts, helping legacy boards meet thermal budgets. The UV window also permits rapid design iteration during board bring-up, where decode maps change frequently during firmware development.

🔧

Glue Logic Replacement for Discrete 74-Series ICs

A single EP1810GI-45 can functionally replace an entire board section of discrete 74LS244, 74LS245, 74LS138, 74LS151, and 74LS374 chips, freeing PCB area and reducing the bill-of-materials count on legacy logic boards. The 24 macrocells comfortably accommodate 8 to 12 small SSI/MSI functions, while the 45 ns tpd preserves the original timing budgets of 74LS-grade designs. CMOS technology reduces the quiescent current draw by approximately 80% versus the bipolar 74LS families it replaces, an attractive feature for legacy systems on tight thermal budgets. The ceramic PGA package is footprint-compatible with the original 68-pin through-hole discrete logic layouts.

🏭

State Machine Controllers

With 48 flip-flops and 24 macrocells, the EP1810GI-45 is well suited for implementing Moore and Mealy state machines with up to several dozen states for sequencer, controller, and protocol-handshake applications. The 45 ns tpd provides comfortable timing margin for asynchronous state transitions and edge-detect sequencing in legacy industrial and aerospace sequencers. The UV-erasable window enables engineering teams to iterate on state-machine designs during prototype validation without re-spun programmers. Rochester Electronics' authorized silicon ensures long-term availability for aerospace sequencer designs that may be in service for decades.

🌐

I/O Expansion and Bus Multiplexing

The EP1810GI-45's macrocell-rich architecture makes it ideal for I/O expansion, bus multiplexing, and signal routing in legacy microcomputer systems where multiple peripheral buses share a common processor bus. Its 45 ns tpd handles bus-turnaround timing comfortably for MHz-class microprocessor systems, while the CMOS process keeps power dissipation low in continuously-active I/O-mux roles. The CPGA-68 ceramic package is footprint-compatible with older discrete-logic I/O-mux boards, enabling drop-in modernization. Rochester Electronics' franchise distribution keeps these parts in stock for long-lifecycle industrial I/O systems.

✈️

Military and Aerospace Legacy Avionics

The ceramic CPGA-68 package, military temperature screening, and known Altera Classic EPLD silicon make the EP1810GI-45 a long-standing choice for military and aerospace avionics, ground-support equipment, and defense electronics where a UV-erasable PLD with deterministic timing is preferred over reprogrammable flash-based logic. Its 45 ns tpd aligns with the conservative timing margins typical of avionics designs, and Rochester Electronics' military-screened variants (e.g., EP1810GM-45) extend the operating temperature range. The long-life cycle of military platforms - often 20 to 30 years - is supported by Rochester's authorized Classic EPLD franchise stocking program, which guarantees continued silicon availability for legacy defense designs.

Recommended Products Summary

EP1810GC-35 Altera Used in: Legacy Industrial Control Logic, Microprocessor Bus Address Decode, Glue Logic Replacement for Discrete 74-Series ICs, I/O Expansion and Bus Multiplexing 5M240ZT100C5N Altera Used in: Legacy Industrial Control Logic SN74LS138 Texas Instruments Used in: Legacy Industrial Control Logic 5M80ZT100C5N Intel Used in: Microprocessor Bus Address Decode AM8086 Legacy microprocessor for which EP1810GI-45 commonly performs address decoding Used in: Microprocessor Bus Address Decode 5M570ZT100C5N Intel Used in: Glue Logic Replacement for Discrete 74-Series ICs SN74LS244 Octal buffer that EP1810GI-45 can replace functionally Used in: Glue Logic Replacement for Discrete 74-Series ICs EP1810GM-45 Military temperature grade variant for aerospace state machines Used in: State Machine Controllers, Military and Aerospace Legacy Avionics 5M1270ZF256I5N Altera Used in: State Machine Controllers 5M570ZM100C5N Altera Used in: I/O Expansion and Bus Multiplexing SN74LS245 Bus transceiver that EP1810GI-45 can replace functionally Used in: I/O Expansion and Bus Multiplexing EP1810GM-35 Military grade, faster 35 ns tpd variant for tighter timing margins Used in: Military and Aerospace Legacy Avionics 5CSXFC5C6U23I7N Intel Used in: Military and Aerospace Legacy Avionics
What is the EP1810GI-45?
The EP1810GI-45 is an Altera Classic EPLD (UV-erasable programmable logic device) with 24 macrocells, 48 flip-flops, and a 45 ns propagation delay, packaged in a 68-pin ceramic Pin Grid Array with a quartz erasure window. According to the Altera Classic EPLD datasheet referenced by FPGAkey and Rochester Electronics, it is one of the original macrocell-based EPLDs intended for glue logic, bus decoding, and state-machine replacement of 74-series discrete logic.
What package does the EP1810GI-45 come in?
The EP1810GI-45 ships in a 68-pin ceramic Pin Grid Array (CPGA-68) with an integrated UV-transparent quartz window for erasure. The ceramic CPGA is a through-hole package and is not RoHS compliant; designers targeting modern lead-free assemblies should evaluate surface-mount CPLDs in equivalent logic-capacity footprints.
How many macrocells and flip-flops does EP1810GI-45 have?
The EP1810GI-45 provides 24 dedicated macrocells and 48 flip-flops (two flip-flops per macrocell in the Classic EPLD family). This logic capacity is sufficient for typical glue-logic, address-decoding, and state-machine applications in legacy microprocessor systems.
What is the propagation delay of EP1810GI-45?
The EP1810GI-45 has a tpd (pin-to-pin propagation delay) of 45 ns, as indicated by the -45 speed grade suffix. The faster -35 variant (EP1810GC-35 / EP1810GI-35) reduces this delay to 35 ns at typically higher cost and power; both share the same Classic EPLD macrocell architecture.
Is the EP1810GI-45 still in production?
No, the EP1810GI-45 is obsolete and no longer manufactured by Altera on the original production line. Rochester Electronics, an authorized Altera franchise partner, continues to distribute remaining factory stock and licensed replicas of Classic EPLD silicon to support long-lifecycle industrial, military, and aerospace customers.
Where can I buy EP1810GI-45 today?
The EP1810GI-45 is available today from Rochester Electronics via DigiKey (part number 12610158), LCSC Electronics (C3273078), and several authorized franchise distributors. Pricing as of 2026-09-06 starts at approximately $88.40 for qty-1 and decreases at higher break quantities; lead time is generally stock-to-immediate for small quantities through Rochester Electronics.
What is the price of EP1810GI-45?
As of 2026-09-06, EP1810GI-45 list pricing on LCSC starts at approximately $88.40 USD per unit at qty-1, with volume breaks down to roughly $56 USD at 1000-piece quantities through Rochester Electronics. Pricing varies across distributors; Octopart and DigiKey both index current stock and franchised pricing.
What is the lead time for EP1810GI-45?
Rochester Electronics ships EP1810GI-45 stock-to-immediate for small quantities as of 2026-09-06 through DigiKey and Octopart listings. For 1000-piece or larger orders, lead time depends on remaining Rochester wafer-bank inventory and may extend to several weeks; check distributor APIs (DigiKey, Mouser, LCSC) for real-time stock visibility.
Is EP1810GI-45 in stock at authorized distributors?
Yes, EP1810GI-45 is currently listed as in stock at Rochester Electronics on DigiKey (part 12610158) and on LCSC Electronics (C3273078) as of 2026-09-06. Inventory fluctuates because the part is end-of-life on the original Altera line and is now supplied through Rochester's authorized Classic EPLD franchise program.
EP1810GI-45 vs EP1810GC-35 - which is faster?
The EP1810GC-35 is faster, with a 35 ns propagation delay versus the EP1810GI-45's 45 ns. Both share the same 24-macrocell Classic EPLD architecture and the same 68-pin ceramic PGA package outline; choosing between them is a speed-versus-cost trade-off - the -45 grade is more available at lower price, the -35 grade is faster but scarcer.
When should I choose EP1810GI-45 over a modern CPLD?
Choose EP1810GI-45 when maintaining a legacy Altera Classic EPLD design, when a ceramic-packaged UV-erasable PLD is required (military, aerospace, long-lifecycle industrial), or when bitstream-erase-and-reprogram security is needed during prototyping. For new designs, modern surface-mount CPLDs in QFP/BGA packages with similar macrocell counts offer better RoHS compliance, lower cost, and higher speed.
Can EP1810GC-35 replace EP1810GI-45?
Yes, the EP1810GC-35 is a drop-in functional upgrade of the EP1810GI-45 in the same 68-pin ceramic PGA package with the same 24 macrocells; only the speed grade differs (35 ns versus 45 ns). Existing board layouts, programmers, and JEDEC fuse-map designs written for the EP1810GI-45 will operate on the EP1810GC-35 without modification.
What is the best drop-in replacement for EP1810GI-45?
The best drop-in replacement for the EP1810GI-45 is the EP1810GC-35, the same Altera Classic EPLD in the same 68-pin ceramic PGA package but with a faster 35 ns speed grade. Both are still distributed by Rochester Electronics; for new designs, consider modern Altera/Intel MAX II CPLDs such as the EPM240T100C5N in a 100-pin TQFP as a logic-equivalent alternative.
Where can I download the EP1810GI-45 datasheet PDF?
The Altera Classic EPLD EP1810GI-45 datasheet is hosted on FPGAkey at https://www.fpgakey.com/altera-parts/ep1810gi-45, with mirrors available through Rochester Electronics and on the Altera/Intel documentation archive. The datasheet covers macrocell architecture, JTAG/programming waveforms, AC timing (including the -45 ns tpd specification), and the CPGA-68 pinout with UV-window dimensions.
Where can I find the EP1810GI-45 pinout?
The EP1810GI-45 pinout for the 68-pin ceramic PGA is published in the Altera Classic EPLD datasheet hosted on FPGAkey and Rochester Electronics' part record. Pin 1 is conventionally marked on the package; the pinout lists macrocell I/O assignments, dedicated inputs, VCC, and GND pins for the 24-macrocell Classic EPLD die.

Engineering reference data for EP1810GI-45 — comparison, design guidance, and compliance information.

Selection Guide

Choose EP1810GI-45 when maintaining a legacy Altera Classic EPLD design that requires 45 ns propagation delay, when a Rochester Electronics franchised Altera part is acceptable for the supply chain, or when the 45 ns speed grade's cost advantage outweighs the speed benefit of the -35 variant. Choose EP1810GC-35 instead when tighter address-decode or state-machine timing margins are needed (35 ns tpd, same 68-pin ceramic PGA footprint, drop-in upgrade). Choose EP1810GM-45 or EP1810GM-35 for military temperature grade designs. Choose EP1810LC-35 for low-power applications. For new designs, prefer modern Altera/Intel MAX II or MAX V CPLDs from the Site MPN list (such as EPM240T100C5N, 5M80ZT100C5N, or 5M570ZT100C5N) which offer higher density, lower power, surface-mount QFP/BGA packages, and RoHS compliance. All five alternative MPNs share the same CPGA-68 ceramic PGA footprint as the EP1810GI-45, enabling drop-in PCB compatibility for legacy through-hole designs.

Comparison with Alternatives

Parameter This Product EP1810GC-35 EP1810GC-35AB EP1810LC-35 EP1810GM-35 EP1810GM-45
Brand Altera Altera Altera Altera Altera Altera
Package CPGA-68 CPGA-68 (same) CPGA-68 (same) CPGA-68 (same) CPGA-68 (same) CPGA-68 (same)
Propagation Delay (tpd) 45 ns 35 ns (-22%) 35 ns (-22%) 35 ns (-22%) 35 ns (-22%) 45 ns (same)
Macrocells 24 24 (same) 24 (same) 24 (same) 24 (same) 24 (same)
Flip-Flops 48 48 (same) 48 (same) 48 (same) 48 (same) 48 (same)
Technology CMOS CMOS CMOS CMOS (low-power) CMOS (military grade) CMOS (military grade)
Operating Temperature [DATA_NEEDED] [DATA_NEEDED] [DATA_NEEDED] Military grade (-55C to +125C) Military grade (-55C to +125C)
UV-Erasable Yes Yes Yes Yes Yes Yes
Lifecycle Status Obsolete (Rochester franchise stock) Obsolete (Rochester franchise stock) Obsolete (Rochester franchise stock) Obsolete (military franchise stock) Obsolete (military franchise stock)

Key Differentiators

  • Same-die, faster -35 grade drop-in upgrade available (vs EP1810GC-35)
  • Military temperature grade variant available in same package (vs EP1810GM-45)
  • Low-power CMOS variant available for power-sensitive designs (vs EP1810LC-35)

Design Notes

Estimated: The EP1810GI-45 must be erased with a UV dose of approximately 30 W·s/cm^2 (watt-seconds per square centimeter) of 254 nm UV light before reprogramming. Insufficient erasure time leaves residual programming charges that cause functional errors and unreliable operation. Use a dedicated UV eraser, not sunlight or fluorescent room light, and confirm erasure by a blank-check read on the programmer before reprogramming.

Estimated: The CPGA-68 ceramic package has a typical theta_JA of approximately 30 C/W in still air. At CMOS EPLD quiescent and dynamic currents, total package dissipation at 5 MHz internal logic toggling remains well below 1 W, so the junction-to-ambient rise is roughly 30 C above ambient - acceptable for commercial temperature operation. For military temperature screening (-55C to +125C), use the EP1810GM-45 or EP1810GM-35 variants that share the same CPGA-68 pinout.

The CPGA-68 package is through-hole and not RoHS compliant; the lead finish is typically SnPb. For lead-free reflow compatibility, choose modern surface-mount CPLDs in the Altera MAX II / MAX V family (for example EPM240T100C5N or 5M80ZT100C5N from the Site MPN list) in TQFP-100 packages. When replacing EP1810GI-45 on a legacy through-hole board, use a PGA-to-PGA adapter or migrate to a daughter-board design.

The EP1810GI-45 requires a dedicated Altera Classic EPLD programmer (e.g., Data I/O or BP Microsystems programmers with EPLD Classic support modules) and a CPGA-68 programming socket. Modern Altera/Intel USB-Blaster programmers do not support the Classic EPLD family - verify programmer compatibility before committing to the EP1810GI-45 in prototype development. JEDEC fuse-map files (.jed) written for EP1810GI-45 are forward-compatible with EP1810GC-35 and EP1810GM-45 in the same package.

Compliance Information

RoHS
Non Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Lead Free
No
Halogen Free
Unknown
Conflict Minerals
Compliant

Ceramic CPGA-68 package is through-hole SnPb, RoHS non-compliant by exemption may apply for military/aerospace. Reach compliant per Rochester Electronics part listing. Not AEC-Q100 qualified; military temperature variants (EP1810GM-45) follow MIL-STD-883 screening rather than automotive AEC-Q100.

Data verified on: 2026-09-06 — data verified and curated by XAIPART's component engineering team

Related Searches

EP1810GI-45 EP1810GI-45 datasheet Altera Classic EPLD EP1810GI-45 EP1810GI-45 pinout CPGA-68 EP1810GI-45 macrocell 24 45ns EP1810GI-45 buy Rochester Electronics EP1810GI-45 price stock distributor EP1810GI-45 vs EP1810GC-35 EP1810GI-45 drop-in replacement Altera Classic EPLD UV erasable PLD EP1810GI-45 lead time Rochester EP1810GI-45 obsolete Altera EPLD

Related Components & Terms

Altera EP1810GI-45 EP1810GC-35 EP1810GC-35AB EP1810LC-35 EP1810GM-35 EP1810GM-45 Rochester Electronics EPLD erasable programmable logic device Classic EPLD PLD programmable logic device CPLD FPGA macrocell flip-flop CPGA-68 ceramic PGA UV-erasable CMOS JEDEC SnPb glue logic address decoding state machine MIL-STD-883
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