EP1C3T144CB - Cyclone FPGA, 3K LEs, TQFP-144 | Intel / Altera
MPN: EP1C3T144CB ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.3 | $6,150.00 |
| 1,000 | $10.85 | $10,850.00 |
Drop-in alternatives for EP1C3T144CB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1C3T144C8N
✅ Drop-In✓ In Stock
$14.1 / Unit
View Datasheet →EP1C3T144C8
✅ Drop-In✓ In Stock
$11.2 / Unit
View Datasheet →EP1C3T144C8NGA
✅ Drop-In✓ In Stock
$14.2 / Unit
View Datasheet →EP1C3T144C7N
✅ Drop-In✓ In Stock
$16.2 / Unit
View Datasheet →EP1C3T144C6N
✅ Drop-In✓ In Stock
$11.94 / Unit
View Datasheet →EP2C5T144C8N
✅ Drop-In📋 Reference alternative (not in catalog)
EP1C3T144CB Maximum Ratings & Electrical Characteristics
| Family | Cyclone |
| Logic Elements | 2,910 |
| M4K RAM Blocks | 13 |
| Embedded Memory (bits) | 58,368 |
| PLLs | 1 |
| Global Clock Networks | 8 |
| Maximum User I/O Pins | 104 |
| Package | TQFP-144 (T144), 22x22 mm |
| Process Technology | 0.13 µm SRAM |
| Configuration Method | SRAM, serial (EPC) or JTAG |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL-2, SSTL-3 |
| Operating Voltage (Core) | 1.5 V |
| Operating Temperature (Commercial) | 0C to +85C |
| Mounting Type | Surface Mount |
| RoHS Status | Contains lead (non-RoHS) |
EP1C3T144CB Pin Configuration
| Pin 1 | I/O — General purpose user I/O (bank 1) |
| Pin 2 | I/O — General purpose user I/O (bank 1) |
| Pin 3 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 4 | I/O — General purpose user I/O (bank 1) |
| Pin 5 | I/O — General purpose user I/O (bank 1) |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — General purpose user I/O (bank 2) |
| Pin 8 | I/O — General purpose user I/O (bank 2) |
| Pin 9 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 10 | I/O — General purpose user I/O (bank 2) |
| Pin 11 | I/O — General purpose user I/O (bank 2) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — General purpose user I/O (bank 3) |
| Pin 14 | DATA0 — Configuration data input |
| Pin 15 | nCONFIG — Configuration control (active low) |
| Pin 16 | DCLK — Configuration clock |
| Pin 17 | nSTATUS — Configuration status (active low) |
| Pin 18 | I/O — General purpose user I/O (bank 3) |
| Pin 19 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 20 | I/O — General purpose user I/O (bank 3) |
| Pin 21 | I/O — General purpose user I/O (bank 3) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — General purpose user I/O (bank 4) |
| Pin 24 | I/O — General purpose user I/O (bank 4) |
| Pin 25 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 26 | I/O — General purpose user I/O (bank 4) |
| Pin 27 | I/O — General purpose user I/O (bank 4) |
| Pin 28 | GND — Ground |
| Pin 29 | I/O — General purpose user I/O (bank 5) |
| Pin 30 | I/O — General purpose user I/O (bank 5) |
| Pin 31 | VCCIO5 — I/O bank 5 supply voltage |
| Pin 32 | I/O — General purpose user I/O (bank 5) |
| Pin 33 | I/O — General purpose user I/O (bank 5) |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — General purpose user I/O (bank 6) |
| Pin 36 | I/O — General purpose user I/O (bank 6) |
| Pin 37 | VCCIO6 — I/O bank 6 supply voltage |
| Pin 38 | I/O — General purpose user I/O (bank 6) |
| Pin 39 | I/O — General purpose user I/O (bank 6) |
| Pin 40 | GND — Ground |
| Pin 41 | I/O — General purpose user I/O (bank 7) |
| Pin 42 | I/O — General purpose user I/O (bank 7) |
| Pin 43 | VCCIO7 — I/O bank 7 supply voltage |
| Pin 44 | I/O — General purpose user I/O (bank 7) |
| Pin 45 | I/O — General purpose user I/O (bank 7) |
| Pin 46 | GND — Ground |
| Pin 47 | I/O — General purpose user I/O (bank 8) |
| Pin 48 | I/O — General purpose user I/O (bank 8) |
| Pin 49 | VCCIO8 — I/O bank 8 supply voltage |
| Pin 50 | I/O — General purpose user I/O (bank 8) |
| Pin 51 | I/O — General purpose user I/O (bank 8) |
| Pin 52 | GND — Ground |
| Pin 53 | VCCINT — Core voltage (1.5 V) |
| Pin 54 | I/O — General purpose user I/O (bank 1) |
| Pin 55 | I/O — General purpose user I/O (bank 1) |
| Pin 56 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 57 | I/O — General purpose user I/O (bank 1) |
| Pin 58 | I/O — General purpose user I/O (bank 1) |
| Pin 59 | GND — Ground |
| Pin 60 | I/O — General purpose user I/O (bank 2) |
| Pin 61 | I/O — General purpose user I/O (bank 2) |
| Pin 62 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 63 | I/O — General purpose user I/O (bank 2) |
| Pin 64 | I/O — General purpose user I/O (bank 2) |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — General purpose user I/O (bank 3) |
| Pin 67 | MSEL0 — Configuration mode select 0 |
| Pin 68 | MSEL1 — Configuration mode select 1 |
| Pin 69 | I/O — General purpose user I/O (bank 3) |
| Pin 70 | I/O — General purpose user I/O (bank 3) |
| Pin 71 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 72 | I/O — General purpose user I/O (bank 3) |
| Pin 73 | GND — Ground |
| Pin 74 | I/O — General purpose user I/O (bank 4) |
| Pin 75 | I/O — General purpose user I/O (bank 4) |
| Pin 76 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 77 | I/O — General purpose user I/O (bank 4) |
| Pin 78 | I/O — General purpose user I/O (bank 4) |
| Pin 79 | GND — Ground |
| Pin 80 | I/O — General purpose user I/O (bank 5) |
| Pin 81 | I/O — General purpose user I/O (bank 5) |
| Pin 82 | VCCIO5 — I/O bank 5 supply voltage |
| Pin 83 | I/O — General purpose user I/O (bank 5) |
| Pin 84 | I/O — General purpose user I/O (bank 5) |
| Pin 85 | GND — Ground |
| Pin 86 | I/O — General purpose user I/O (bank 6) |
| Pin 87 | I/O — General purpose user I/O (bank 6) |
| Pin 88 | VCCIO6 — I/O bank 6 supply voltage |
| Pin 89 | I/O — General purpose user I/O (bank 6) |
| Pin 90 | I/O — General purpose user I/O (bank 6) |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — General purpose user I/O (bank 7) |
| Pin 93 | I/O — General purpose user I/O (bank 7) |
| Pin 94 | VCCIO7 — I/O bank 7 supply voltage |
| Pin 95 | I/O — General purpose user I/O (bank 7) |
| Pin 96 | I/O — General purpose user I/O (bank 7) |
| Pin 97 | GND — Ground |
| Pin 98 | I/O — General purpose user I/O (bank 8) |
| Pin 99 | I/O — General purpose user I/O (bank 8) |
| Pin 100 | VCCIO8 — I/O bank 8 supply voltage |
| Pin 101 | I/O — General purpose user I/O (bank 8) |
| Pin 102 | I/O — General purpose user I/O (bank 8) |
| Pin 103 | GND — Ground |
| Pin 104 | CLK0 — Global clock input 0 / PLL reference |
| Pin 105 | CLK1 — Global clock input 1 |
| Pin 106 | CLK2 — Global clock input 2 |
| Pin 107 | CLK3 — Global clock input 3 |
| Pin 108 | I/O — General purpose user I/O (bank 1) |
| Pin 109 | I/O — General purpose user I/O (bank 1) |
| Pin 110 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 111 | I/O — General purpose user I/O (bank 1) |
| Pin 112 | I/O — General purpose user I/O (bank 1) |
| Pin 113 | GND — Ground |
| Pin 114 | TDI — JTAG test data input |
| Pin 115 | TMS — JTAG test mode select |
| Pin 116 | TCK — JTAG test clock |
| Pin 117 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 118 | I/O — General purpose user I/O (bank 2) |
| Pin 119 | I/O — General purpose user I/O (bank 2) |
| Pin 120 | GND — Ground |
| Pin 121 | TDO — JTAG test data output |
| Pin 122 | I/O — General purpose user I/O (bank 2) |
| Pin 123 | I/O — General purpose user I/O (bank 3) |
| Pin 124 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 125 | I/O — General purpose user I/O (bank 3) |
| Pin 126 | I/O — General purpose user I/O (bank 3) |
| Pin 127 | GND — Ground |
| Pin 128 | VCCINT — Core voltage (1.5 V) |
| Pin 129 | I/O — General purpose user I/O (bank 4) |
| Pin 130 | I/O — General purpose user I/O (bank 4) |
| Pin 131 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 132 | I/O — General purpose user I/O (bank 4) |
| Pin 133 | I/O — General purpose user I/O (bank 4) |
| Pin 134 | GND — Ground |
| Pin 135 | I/O — General purpose user I/O (bank 5) |
| Pin 136 | I/O — General purpose user I/O (bank 5) |
| Pin 137 | VCCIO5 — I/O bank 5 supply voltage |
| Pin 138 | I/O — General purpose user I/O (bank 5) |
| Pin 139 | I/O — General purpose user I/O (bank 5) |
| Pin 140 | GND — Ground |
| Pin 141 | I/O — General purpose user I/O (bank 6) |
| Pin 142 | I/O — General purpose user I/O (bank 6) |
| Pin 143 | VCCIO6 — I/O bank 6 supply voltage |
| Pin 144 | I/O — General purpose user I/O (bank 6) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1C3T144CB is suitable for 6 applications: Industrial Motor Control Glue Logic, Low-Cost Video Format Converter, Customer-Premises Equipment Interface Bridge, Display Controller and LCD Timing Generator, PCIe Endpoint Bridge for Legacy Systems, Educational FPGA Development Board.
Industrial Motor Control Glue Logic
The EP1C3T144CB fits industrial motor-control boards where PWM generation, quadrature decoding, and CAN-bus bridging must be implemented in programmable hardware alongside an MCU. Its 2,910 LEs are sufficient to host a 3-axis PWM/timer block plus a hardware quadrature encoder interface, while the 104 user I/Os accept the encoder, Hall-sensor, and gate-driver signals directly. The single on-chip PLL synthesizes the high-frequency clock for the MCU bus, and the device's LVTTL/LVCMOS tolerance simplifies 3.3V and 5V signal mixing on the same board. Compared with discrete 74-series glue logic this FPGA collapses 30+ packages onto one part, reducing PCB area and improving noise immunity on the noisy motor-drive floor.
Recommended
Low-Cost Video Format Converter
Consumer and prosumer video equipment frequently uses a Cyclone EP1C3T144CB to convert between digital video formats such as ITU-R BT.656, RGB888, and LVDS panel inputs. The 13 M4K RAM blocks act as line buffers and chroma upsamplers, while 104 user I/Os comfortably handle 24-bit video buses plus control signals. The 0.13-µm silicon is fast enough to run pipelined color-space conversion at pixel clock rates above 65 MHz. Designers value the device because Quartus II reference designs provide free IP for BT.656-to-RGB conversion, dramatically shortening time-to-market for low-volume broadcast accessories.
Recommended
Customer-Premises Equipment Interface Bridge
CPE devices such as DSL modems, ONTs, and small-office routers use the EP1C3T144CB as a flexible bus bridge between an ASIC/SoC and PHY chips, providing I2C, SPI, MDIO, and proprietary side-band signal aggregation. Its 104 user I/Os map easily to multi-PHY systems, and the embedded PLL cleans up noisy recovered clocks from the PHY. Because the design is SRAM-based, the bridge can be firmware-upgraded in the field to add new PHY compatibility without re-spinning hardware, which is critical for carrier certifications. Low core power (~100 mW) also helps CPE products meet Energy Star idle budgets.
Recommended
Display Controller and LCD Timing Generator
Embedded display subsystems for industrial HMIs, medical monitors, and kiosk displays rely on the EP1C3T144CB to generate non-standard LCD timings, perform color-depth reduction, and overlay graphical OSD on incoming video. The 2,910 LEs implement timing-state machines and small sprite renderers, while 13 M4K blocks serve as frame-line FIFOs. The single PLL synthesizes the panel pixel clock from any reference frequency with sub-pixel alignment. Compared with fixed-function LCD controller ASICs, the FPGA approach lets the OEM support multiple panel SKUs with one BOM by simply swapping the Quartus programming file.
Recommended
PCIe Endpoint Bridge for Legacy Systems
Legacy telecom and test-and-measurement boards use the EP1C3T144CB as a PCI-to-PCIe protocol bridge, replacing obsolete PCI controller ASICs with a soft PCIe endpoint IP core inside the FPGA. Quartus II ships a free PCIe x1 endpoint core that fits comfortably inside the 2,910 LEs, leaving margin for application logic. The 104 user I/Os provide the legacy 32-bit/33 MHz PCI bus plus side-band signals (INTA#, PME#, etc.). This application is one of the most-documented Cyclone reference designs, and Cyclone's per-LE low cost keeps bridge BOM cost under $20 in production.
Recommended
Educational FPGA Development Board
Universities and hobbyists adopted the EP1C3T144CB as the reference FPGA on early Altera DE0 and Terasic-compatible boards because it provides enough logic and I/O to teach Verilog/VHDL, state machines, and soft-core CPUs (Nios II) at low cost. The TQFP-144 footprint is breadboard-friendly with 0.5 mm pitch, hand-solderable by experienced students. The single PLL introduces clock-management concepts, and the JTAG interface allows free Quartus II Web Edition to program and debug the device without a hardware programmer. Although Cyclone I is now obsolete, many course curricula still use the board because the legacy toolchain remains functional on legacy Windows machines.
Recommended
Recommended Products Summary
Engineering reference data for EP1C3T144CB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1C3T144C8N | EP1C3T144C8 | EP1C3T144C8NGA | EP1C3T144C7N | EP1C3T144C6N | EP2C5T144C8N |
|---|---|---|---|---|---|---|---|
| Package | TQFP-144 (T144) | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Family | Cyclone | Cyclone | Cyclone | Cyclone | Cyclone | Cyclone | Cyclone II |
| Logic Elements | 2,910 | 2,910 | 2,910 | 2,910 | 2,910 | 2,910 | 4,608 |
| Embedded RAM (bits) | 58,368 | 58,368 | 58,368 | 58,368 | 58,368 | 58,368 | 119,808 |
| PLLs | 1 | 1 | 1 | 1 | 1 | 1 | 2 |
| Temperature Grade | Commercial (0C to +85C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | Speed grade 6 (slowest) | Speed grade 8 | Speed grade 8 | Speed grade 8 | Speed grade 7 | Speed grade 6 | Speed grade 8 (Cyclone II) |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.2 V |
Key Differentiators
- Lowest-cost drop-in replacement candidates share the exact same silicon (vs EP1C3T144C8N)
- TQFP-144 package enables hand-solderable prototypes (vs EP2C5T144C8N)
- Wide Quartus II Web Edition toolchain support (vs EP3C5E144C8N)
Design Notes
Estimated: at typical utilization of 70% LEs and 80% RAM blocks with a 65 MHz internal clock, the EP1C3T144CB dissipates approximately 100-150 mW of core power plus I/O bank power. The board must provide a clean 1.5V core supply (VCCINT) and per-bank VCCIO supplies; place 100 nF and 10 µF decoupling capacitors within 5 mm of every VCC pin pair. I/O banks 1-8 each need independent bypass because mixed-voltage standards (3.3V, 2.5V, 1.8V) on different banks are common in Cyclone designs.
The EP1C3T144CB is a SRAM-based FPGA, so the configuration is lost on every power-down. A non-volatile configuration source is mandatory: either an EPCS serial configuration device on the DCLK/DATA0/nCONFIG/nSTATUS pins, or a JTAG programmer. Forgetting to populate MSEL0/MSEL1 pull resistors correctly is a top cause of configuration failure - the datasheet table shows the resistor values needed for each configuration mode (AS, PS, JTAG).
TQFP-144 has a 0.5 mm lead pitch that is hand-solderable but challenging for production reflow without proper land pattern and paste stencil. Use the IPC-7351 nominal land pattern and a 0.15 mm thick stencil with aperture reduction of 10-20%. Place configuration EPROM within 25 mm of the FPGA to keep DCLK/DATA0 traces short; long configuration traces cause bit errors at high DCLK rates. The exposed thermal pad (if present on the specific package variant) must be soldered to a ground pour with thermal vias.
Compliance Information
Cyclone I devices (including EP1C3T144CB) use lead-bearing TQFP packages and are not RoHS-compliant. REACH compliance per legacy Altera product declarations. AEC-Q100 not applicable - this is a logic IC, not an automotive-grade part.
