EP20K400FG672-2 - APEX 20K FPGA 400K Gates 672-BGA | Altera
MPN: EP20K400FG672-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132 | $1,320.00 |
| 100 | $118 | $11,800.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92 | $92,000.00 |
EP20K400FG672-2 Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device that combines a sea of configurable logic blocks (LUTs), programmable interconnect, and I/O cells on a single die. APEX 20K belongs to the hierarchy: FPGA -> programmable logic device -> logic IC -> integrated circuit -> semiconductor. APEX 20K extended Altera's earlier FLEX 10K family by adding MultiCore interconnect and embedded dual-port RAM blocks, and was later superseded by APEX 20KE and the Stratix series.
Key features include a -2 speed grade targeting internal logic clocking, support for multiple I/O standards including LVTTL, LVCMOS, PCI, SSTL, and GTL+, and high-speed interconnect through the MultiCore routing fabric. The EP20K400 provides dedicated clock, clock-enable, and clear signals per Logic Array Block (LAB), supporting efficient pipelined designs.
Technical depth: the -2 speed grade positions this part between the -1 (faster) and -3 (slower) grades of the same die, balancing timing margin and cost. The device is built on a 0.18-micron CMOS process and operates from a 2.5 V core supply with separate VCCIO bank supplies for mixed-voltage I/O.
Typical applications include telecommunications line cards, ASIC prototyping, complex state-machine controllers, and high-speed data path glue logic. The APEX 20K family was commonly used in designs that needed significant on-chip memory without an external SRAM.
When designing with EP20K400FG672-2, engineers should use the legacy Altera Quartus II (or MAX+PLUS II for backward compatibility) toolchain, as APEX 20K is no longer supported by Quartus Prime Pro Edition. Plan migration to APEX 20KE or Stratix for new designs.
This page synthesizes distributor availability, same-family drop-in alternatives, and practical migration guidance not consolidated in any single manufacturer document.
Drop-in alternatives for EP20K400FG672-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FG672-2 (same form factor and footprint) — differing in Operating Temperature, Process Technology, Family, Package, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400EFC672-2
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K400EFC672-2N
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFI672-2N
✅ Drop-In✓ In Stock
$105 / Unit
View Datasheet →EP20K400FC672-2
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFC672-2X
✅ Drop-In✓ In Stock
$118.9 / Unit
View Datasheet →EP20K400FG672-2 Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Maximum System Gates | 1,060,000 (typ 400,000) |
| Logic Elements | 21,500 |
| Embedded System Blocks (ESBs) | 488 |
| Maximum RAM Bits | 212,992 |
| Macros / Logic Elements | 16,640 |
| Maximum User I/O | 488 |
| Speed Grade | -2 |
| Package | 672-ball FineLine BGA (FG672) |
| Core Voltage | 2.5 V (2.375 V to 2.625 V) |
| Process Technology | 0.18 micron CMOS |
| Operating Temperature | 0C to +85C (commercial) |
| Propagation Delay | 3.1 ns (typ) |
| Mounting Type | Surface Mount |
| RoHS Status | non_compliant (legacy) |
| Toolchain Support | Quartus II / MAX+PLUS II only |
EP20K400FG672-2 672-ball fineline bga (fg672) Pin Configuration Guide
Pin configuration for EP20K400FG672-2 (672-ball fineline bga (fg672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FG672-2.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FG672-2 is suitable for 6 applications: Telecommunications Line Card Logic, ASIC Prototyping and Emulation, Industrial Control and State Machines, High-Speed Data Path Glue Logic, Medical Imaging Pipeline (Legacy), Test and Measurement Instrumentation.
Telecommunications Line Card Logic
The EP20K400FG672-2 fits telecom line-card applications because it delivers 400K system gates with 488 user I/O and 212 Kbits of on-chip dual-port RAM, allowing designers to consolidate framer, mapper, and traffic-manager glue logic into a single BGA. Its 0.18 micron CMOS process and 2.5 V core operation meet the power and thermal envelopes of dense central-office line cards, while the 488-ball FineLine BGA enables multi-bank I/O routing for LVTTL, LVCMOS, and GTL+ interfaces to PHY devices. Compared to discrete ASIC + SRAM partitioning, this APEX 20K device reduces BOM cost and simplifies ECO turns during protocol updates such as SONET/SDH or early Ethernet revisions.
Recommended
ASIC Prototyping and Emulation
For ASIC prototyping, the EP20K400FG672-2 supplies 21,500 logic elements and 488 ESBs that map cleanly onto gate-array ASICs of similar density, allowing RTL validation before tape-out. The 672-ball FineLine BGA exposes enough I/O to mirror full ASIC pinouts, while the APEX 20K MultiCore interconnect minimizes routing congestion when partitioning large ASIC blocks across multiple FPGAs. Quartus II design entry supports incremental compile, making it feasible to iterate gate-level netlists against the original ASIC RTL.
Recommended
Industrial Control and State Machines
In industrial control, the EP20K400FG672-2 implements complex state machines, encoder/decoder logic, and protocol bridges without an external MCU. Its 488 ESBs allow distributed product-term logic that mimics PAL/PLA behavior, while the 212 Kbits of dual-port SRAM buffer fast sensor data streams. The -2 speed grade delivers internal timing margins suitable for deterministic control loops at industrial clock rates, and the 0 to 85C commercial temperature range covers most factory-floor enclosures.
Recommended
High-Speed Data Path Glue Logic
The EP20K400FG672-2 is well suited for high-speed data-path bridging between network processors, FIFOs, and serializer/deserializer devices. Its 488 I/O supports multiple LVTTL/LVCMOS buses simultaneously, and the APEX 20K MultiCore routing fabric maintains tight timing margins across pipelined datapaths. On-chip dual-port RAM in 488 ESBs provides the buffering required for packet header inspection or CRC computation without external SRAM, reducing board complexity and BOM cost.
Recommended
Medical Imaging Pipeline (Legacy)
Long-lifecycle medical imaging platforms use the EP20K400FG672-2 to implement pixel pipelines and frame-buffer arbitration. Its 212 Kbits of on-chip dual-port SRAM act as line buffers for ultrasound or X-ray front-ends, while 21,500 logic elements handle pixel-rate image processing. The 672-ball BGA supports the high pin count required to drive parallel ADC/DAC interfaces, and the -2 speed grade provides the deterministic internal timing needed for pixel-clock domains.
Recommended
Test and Measurement Instrumentation
Test and measurement instruments use the EP20K400FG672-2 for waveform generation, pattern matching, and protocol-aware triggering. The 488 ESBs implement lookup tables and counters that drive arbitrary waveform synthesizers, while the 488 user I/O handle parallel bus capture from logic analyzers. The -2 speed grade supports clock rates typical of mid-tier instrumentation, and the APEX 20K ESBs offer the product-term logic useful for state-machine-based triggering logic.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FG672-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400EFC672-2 | EP20K400EFC672-2N | EP20K400EFI672-2N | EP20K400FC672-2 | EP20K400EFC672-2X |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-BGA (FG672) | 672-BGA (FC672) - same footprint | 672-BGA (FC672) - same footprint | 672-BGA (FI672) - same footprint | 672-BGA (FC672) - same footprint | 672-BGA (FC672) - same footprint |
| Family | APEX 20K | APEX 20KE | APEX 20KE | APEX 20KE | APEX 20K | APEX 20KE |
| Maximum System Gates | 1,060,000 | 1,060,000 | 1,060,000 | 1,060,000 | 1,060,000 | 1,060,000 |
| Logic Elements | 21,500 | 21,500 | 21,500 | 21,500 | 21,500 | 21,500 |
| ESBs (Embedded System Blocks) | 488 | 488 | 488 | 488 | 488 | 488 |
| Maximum User I/O | 488 | 488 | 488 | 488 | 488 | 488 |
| Speed Grade | -2 | -2 | -2 | -2 | -2 | -2 |
| Temperature Grade | Commercial (0C to 85C) | Commercial | Commercial | Industrial | Commercial | Commercial |
Key Differentiators
- FineLine BGA pitch (1.27 mm) vs standard PBGA (1.5 mm) (vs EP20K400FC672-2)
- Enhanced I/O standard support in APEX 20KE (vs EP20K400FC672-2)
- Industrial temperature variant option (vs EP20K400FC672-2)
Design Notes
APEX 20K is no longer supported by Quartus Prime Pro Edition. Use Quartus II 13.0sp1 or MAX+PLUS II 10.2 for design entry. Toolchain drift is the most common reason legacy EP20K400 boards fail bring-up - confirm the JTAG programmer and software version match the bitstream format before debugging. Estimated: Quartus II is required for Place-and-Route of APEX 20K because MAX+PLUS II supports only FLEX 6000 / 8000 / 10K generation.
The 672-ball FineLine BGA exposes the die primarily through the central ball grid. Place a thermal via array under the package center to conduct heat into an inner ground plane; without this, junction temperature can rise 20-30C above ambient under full logic utilization. The APEX 20K does not integrate an on-die thermal diode; use the package thermal pad resistance of approximately 0.4 C/W and size your copper pour to keep Tj below 125C. Estimated: thermal pad resistance derived from Altera package thermal characterization notes.
Use a 4-6 layer PCB with dedicated VCC (2.5 V) and VCCIO (per bank) planes. Decouple each VCC/VCCIO ball pair with a 0.1 uF X7R ceramic plus a 10 uF tantalum or polymer bulk capacitor placed within 5 mm of the package. The 1.27 mm ball pitch of the FineLine BGA demands 0.1 mm (4 mil) trace-and-space rules at the fan-out layer. Microvia stacks on the inner balls help minimize escape routing congestion.
Compliance Information
APEX 20K is a legacy Altera family manufactured on 0.18 micron CMOS before RoHS transition; most FG672-2 stock is non-RoHS lead-bearing. Lead-free APEX 20KE variants (suffix 'N' or 'X') provide RoHS compliance in the same footprint.
