EP2AGX190FF35I5 - Arria II GX FPGA, 181165 LE, 612 I/O | Intel
MPN: EP2AGX190FF35I5 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2204.17 | $2,204.17 |
| 10 | $2085 | $20,850.00 |
| 100 | $1950 | $195,000.00 |
| 500 | $1820 | $910,000.00 |
| 1,000 | $1700 | $1,700,000.00 |
EP2AGX190FF35I5 Overview
An FPGA (Field-Programmable Gate Array) is a class of programmable logic device that lets designers configure arbitrary digital circuits through SRAM-based configuration memory. Within the broader semiconductor taxonomy, FPGAs sit alongside ASICs and CPLDs as the main forms of hardware-level programmable logic; Arria II GX is positioned as Intel's mid-range, transceiver-rich family that bridges between Cyclone V (low-cost) and Stratix IV (high-performance) families, aimed at cost-sensitive applications that still require multi-gigabit serial links.
Key features of the EP2AGX190FF35I5 include integrated transceivers supporting multi-gigabit serial protocols, hard PCIe Gen1/Gen2 IP blocks, embedded memory blocks totaling 10.18 Mbits, dedicated DSP blocks for high-throughput signal processing, and a large user-I/O count (612) which supports wide parallel interfaces to external memories such as DDR2/DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II. The industrial-grade speed-grade 5 designation means timing closure is rated for -40 C to +100 C ambient operation, which is suitable for telecom, industrial imaging, and military/aerospace subsystems.
The 40 nm process node provides a useful balance between static and dynamic power consumption; the -I5 speed grade is the slowest in the Arria II GX family, trading peak Fmax for lower quiescent power and improved timing margin. The 1152-ball FC-FBGA package uses flip-chip BGA technology with a land-grid pitch suited to high-density PCB designs that require multiple signal layers and a continuous ground/power plane beneath the device.
Typical applications for the EP2AGX190FF35I5 include wireless baseband processing, high-definition video broadcast equipment, medical imaging pipelines, military radar and signal-intelligence front-ends, and PCIe Gen2 host-bus adapter cards. Designers typically pair the part with external DDR3 SODIMMs, Flash configuration memories (EPCS), and clock-generation PLLs to form a complete embedded signal-processing subsystem.
When designing with this FPGA, plan PCB stack-up carefully: 1152 balls at fine pitch demand microvia technology, a 1 oz copper power plane, and matched-length trace tuning for the transceiver channels. Use Intel Quartus II as the design entry, synthesis, place-and-route, and timing-analysis tool; Quartus II is mandatory for transceiver IP configuration and pin planning on Arria II GX devices.
This page synthesizes distributor pricing snapshots, same-package alternatives, and practical Quartus II design-flow notes that go beyond the device datasheet, helping procurement and FPGA engineers make informed sourcing and substitution decisions.
Drop-in alternatives for EP2AGX190FF35I5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX190FF35I5 (same form factor and footprint) β differing in Package, Speed Grade, Mounting Type, RoHS Status, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX190FF35C6N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX190FF35I3N
β Drop-Inβ In Stock
$1190 / Unit
View Datasheet βEP2AGX190FF35I3G
β Drop-Inβ In Stock
$1840 / Unit
View Datasheet βEP2AGX190FF35C6G
β Drop-Inβ In Stock
$188 / Unit
View Datasheet βEP2AGX190FF35C5G
β Drop-Inβ In Stock
$1245 / Unit
View Datasheet βEP2AGX190FF35C4G
β Drop-Inβ In Stock
$2350 / Unit
View Datasheet βEP2AGX190FF35I5 Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Logic Elements (LE) | 181165 |
| Embedded Memory Bits | 10177536 |
| User I/O Count | 612 |
| Process Technology | 40 nm |
| Core Voltage | 0.9 V |
| Package | 1152-ball FC-FBGA (Flip-Chip BGA) |
| Speed Grade | 5 (slowest in family, lower power) |
| Operating Temperature Grade | Industrial (-40 C to +100 C ambient) |
| Maximum User Frequency | 500 MHz |
| PCIe Hard IP | PCIe Gen1/Gen2 hard IP blocks (per family feature) |
| Configuration Memory | SRAM-based, supports EPCS serial Flash loaders |
| Mounting Type | Surface Mount (BGA, reflow soldering required) |
| RoHS Status | Compliant (per Intel product page) |
| Lead-Free | Yes (per Intel product page) |
EP2AGX190FF35I5 1152-ball fc-fbga (flip-chip bga) Pin Configuration Guide
Pin configuration for EP2AGX190FF35I5 (1152-ball fc-fbga (flip-chip bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX190FF35I5.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX190FF35I5 is suitable for 6 applications: Wireless Baseband Processing, High-Definition Video Broadcast Equipment, Medical Imaging Pipelines, Military Radar and SIGINT Front-Ends, PCIe Gen2 Host-Bus Adapter Cards, Industrial Machine Vision Systems.
Wireless Baseband Processing
The EP2AGX190FF35I5's 181165 logic elements and 10.18 Mbits of embedded memory make it well suited for wireless baseband signal processing chains such as LTE small-cell PHY layers, WiMAX demodulators, and proprietary point-to-point radio links. The integrated multi-gigabit transceivers support CPRI and OBSAI fronthaul interfaces to remote radio heads, while the 612 user I/Os connect to DDR3 SDRAM buffers and high-speed ADCs/DACs. Speed grade 5 timing is comfortable for typical baseband sample rates up to ~245.76 MHz, and the industrial temperature grade ensures outdoor base-station reliability across -40 C to +100 C ambient. Pair with an EPCQ serial Flash and a CDCE6214 PLL for a complete radio unit.
Recommended
High-Definition Video Broadcast Equipment
Broadcast video routers, multi-format format converters, and 3G-SDI/HD-SDI crosspoint switches benefit from the EP2AGX190FF35I5's large logic capacity and high I/O count, which let designers implement wide video crosspoints, color-space converters, and frame synchronizers on a single device. The 612 user I/Os comfortably accept 60+ HD-SDI input streams plus ancillary data, while the 10.18 Mbit embedded memory holds multiple line and frame buffers. Speed grade 5 is sufficient for SDI rates up to 3 Gbps (1080p60), and the industrial temperature grade supports both indoor studio and outdoor truck-mounted broadcast installations.
Recommended
Medical Imaging Pipelines
Ultrasound beamformers, CT image reconstruction engines, and MRI RF receiver front-ends can leverage the EP2AGX190FF35I5's high DSP density and multi-gigabit transceiver links to digital back-end processing ASICs. The 181165 logic elements and 10.18 Mbit block RAM hold channelization coefficients and beamformed line buffers, while the 612 I/Os interface to LVDS ADC arrays (typically 12-16 channels at 14-16 bit, 65-80 MSPS). The industrial temperature grade and -40 C to +100 C ambient rating support both portable cart-based and fixed-room imaging installations.
Recommended
Military Radar and SIGINT Front-Ends
Phased-array radar beam-steering controllers and signal-intelligence (SIGINT) digital receivers often use the EP2AGX190FF35I5 because it combines transceiver-rich I/O, large logic capacity, and an industrial temperature grade suited to military airborne and ground-mobile environments. The 612 user I/Os connect to multi-channel ADC/DAC mezzanines and DDR3 SODIMM banks, while the embedded DSP blocks implement FFT, channelization, and pulse-compression kernels. Speed grade 5 timing closes comfortably at sample rates up to 200 MHz, and the flip-chip BGA package provides robust thermal performance under conduction-cooled chassis.
Recommended
PCIe Gen2 Host-Bus Adapter Cards
High-performance PCIe Gen2 host-bus adapter cards (HBAs) and FPGA accelerator cards use the EP2AGX190FF35I5 as the main processing device, leveraging its hard PCIe Gen1/Gen2 IP block and multi-gigabit transceivers for upstream host connectivity. The 181165 logic elements support DMA engines, NVMe controller logic, or custom acceleration kernels, while 612 user I/Os expose multiple external memory channels (DDR3/QDR-IV) and high-speed serial links (10 GbE, SATA, SAS). Speed grade 5 easily closes PCIe Gen2 timing at 5 Gbps, and the industrial temperature grade supports dense accelerator rack deployments.
Recommended
Industrial Machine Vision Systems
Multi-camera machine-vision inspection systems in factory automation use the EP2AGX190FF35I5 to aggregate and process Camera Link, CoaXPress, or GigE Vision streams in real time. The 181165 logic elements implement image pre-processing, blob detection, and pattern-matching kernels, while 612 user I/Os drive multi-channel LVDS camera interfaces and DDR3 frame buffers. The industrial temperature grade (-40 C to +100 C) supports factory-floor environments without active cooling, and speed grade 5 timing easily meets typical Camera Link clock rates of 85 MHz.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX190FF35I5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX190FF35C6N | EP2AGX190FF35I3N | EP2AGX190FF35I3G | EP2AGX190FF35C6G | EP2AGX190FF35C5G | EP2AGX190FF35C4G |
|---|---|---|---|---|---|---|---|
| Package | 1152-BBGA FCBGA | 1152-BBGA FCBGA - same | 1152-BBGA FCBGA - same | 1152-BBGA FCBGA - same | 1152-BBGA FCBGA - same | 1152-BBGA FCBGA - same | 1152-BBGA FCBGA - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | Arria II GX | Arria II GX - same | Arria II GX - same | Arria II GX - same | Arria II GX - same | Arria II GX - same | Arria II GX - same |
| Logic Elements | 181165 | 181165 - same | 181165 - same | 181165 - same | 181165 - same | 181165 - same | 181165 - same |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +85C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | 5 (slowest, lower power) | 6 (fastest) | 3 (fastest industrial) | 3 (fastest industrial) | 6 (fastest) | 5 (same as this product) | 4 |
| Embedded Memory Bits | 10177536 | 10177536 - same | 10177536 - same | 10177536 - same | 10177536 - same | 10177536 - same | 10177536 - same |
| User I/O Count | 612 | 612 - same | 612 - same | 612 - same | 612 - same | 612 - same | 612 - same |
| Lead-Free Suffix | No (I5 only) | No (N suffix) | No (N suffix) | Yes (G suffix) | Yes (G suffix) | Yes (G suffix) | Yes (G suffix) |
Key Differentiators
- Industrial temperature grade with full -40 C to +100 C ambient support (vs EP2AGX190FF35C6N)
- Lowest power speed grade 5 in the family (vs EP2AGX190FF35I3G)
- Same 1152-ball FC-BGA footprint across all EP2AGX190FF35 variants (vs EP2AGX190EF29 series)
Design Notes
The 1152-ball FC-BGA package requires a high-density PCB stack-up: 1.0 mm or finer ball pitch, microvia (laser-drilled) technology, at least 8 signal layers plus 4 power/ground planes, and a continuous ground pad under the device for thermal spreading. Use a 1 oz copper power plane directly under the BGA to keep the core 0.9 V supply impedance below 1 mOhm. Reference Intel AN 583 'Designing with Arria II GX' for full layout guidelines including length-matched transceiver routing.
Estimated: at full resource utilization and ~10 W internal dissipation, the FC-BGA junction-to-ambient thermal resistance (theta_JA) is ~6 C/W with 6 m/s airflow on a JEDEC JESD51 test board, resulting in a 60 C junction temperature rise above ambient. For industrial-temperature operation up to +100 C ambient, designers must either guarantee airflow, use a heatsink with thermal interface material, or mount to a cold-plate chassis conduction cooler. Always verify thermal performance in the final enclosure, not just on the development board.
Three frequent pitfalls in Arria II GX designs: (1) selecting speed grade 5 when the design requires >300 MHz Fmax - choose speed grade 3 or 4 instead; (2) omitting the dedicated PLL reference clock for the transceiver block, which prevents the multi-gigabit links from locking; (3) configuring the wrong EPCS/EPCQ serial Flash loader bitstream format, which causes configuration failures on power-up. Always run TimeQuest timing analysis in Quartus II after place-and-route, and always verify configuration via the JTAG boundary-scan before relying on the Flash loader.
Match transceiver channel traces within 0.127 mm (5 mil) length tolerance for data rates above 5 Gbps, and keep AC-coupling capacitors within 5 mm of the receiver pins. Use a continuous reference ground plane on layer 2 beneath all high-speed serial traces; never route over a plane split. Reference Intel AN 542 'High-Speed Board Design' for the full set of channel-layout guidelines including via stub length, AC-coupling capacitor selection, and connector pinout recommendations.
Compliance Information
RoHS and REACH compliant per Intel product page. AEC-Q100 not applicable (FPGAs are not automotive qualified per AEC-Q100; equivalent automotive-grade parts would be in the Arria V or Cyclone V family). Lead-free confirmed; halogen-free status not stated on the verified product page.
