EP2AGX190FF35C4G - Arria II GX FPGA 190K LE | Intel | 1152-FCBGA
MPN: EP2AGX190FF35C4G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2695 | $26,950.00 |
| 25 | $2580 | $64,500.00 |
| 50 | $2475 | $123,750.00 |
| 100 | $2350 | $235,000.00 |
EP2AGX190FF35C4G Overview
An FPGA (Field Programmable Gate Array) is a semiconductor device built around a matrix of configurable logic blocks (CLBs) connected via programmable interconnect. FPGAs sit in the programmable logic hierarchy between CPLDs (smaller, simpler) and ASICs (larger, higher-density, but fixed-function), and are widely used for digital signal processing, protocol bridging, and hardware acceleration. The Arria II GX family targets mid-range, transceiver-rich designs requiring a balance of logic density, DSP capability, and power efficiency.
Key features include 190K equivalent logic elements (LEs), dedicated hard memory controllers, and 8-input adaptive logic modules (ALMs). The 12 full-dupight transceiver channels support data rates from 600 Mbps to 6.375 Gbps, with built-in PCIe Gen1/Gen2 hard IP blocks, CMU, and channel equalization. The 1152-FCBGA package provides a thermal resistance suitable for industrial thermal envelopes with proper PCB thermal design.
The Arria II GX architecture uses a 40nm low-power process and provides transceivers with superior signal integrity through adaptive equalization and pre-emphasis. Hard IP blocks for PCIe Gen2, Serial RapidIO, and 10 Gigabit Ethernet reduce logic consumption and simplify timing closure. Embedded DSP blocks deliver up to 600 GMACS of processing throughput for high-performance DSP pipelines.
Typical applications include high-speed serial interface bridging, wireless baseband processing, video broadcasting infrastructure, and PCI Express endpoint cards. The combination of transceiver density, on-chip memory bandwidth, and dedicated PCIe hard IP makes it well suited for protocol bridging and high-throughput data acquisition.
When designing with this device, ensure the PCB BGA fanout and stackup meet the FCBGA escape requirements and the reference design guidelines for transceiver channels. Use the Quartus II development environment (supported releases) for synthesis, place-and-route, and SignalTap logic analysis. Power estimation should be performed early using the Quartus PowerPlay analyzer to size the core and transceiver supplies correctly.
This page synthesizes distributor pricing from DigiKey and Mouser, drop-in same-family alternatives, and practical FPGA design guidance that goes beyond the manufacturer datasheet summary.
Drop-in alternatives for EP2AGX190FF35C4G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX190FF35C4G (same form factor and footprint) β differing in Package, Speed Grade, Number of Transceivers, Mounting Type, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX260FF35C4G
β Drop-Inβ In Stock
$1420 / Unit
View Datasheet βEP2AGX125FF35C4G
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX190FF35C4N
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX190EF29C4G
β Drop-Inβ In Stock
$2510 / Unit
View Datasheet βXC6VLX195T-2FF1156C
β Drop-Inπ Reference alternative (not in catalog)
EP2AGX190FF35C4G Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Logic Elements | 181,165 |
| Equivalent Logic Elements | 190,000 |
| Embedded Memory (bits) | 10,177,536 |
| Embedded 18x18 Multipliers | 612 |
| Transceiver Channels | 12 (up to 6.375 Gbps) |
| Maximum Transceiver Data Rate | 6.375 Gbps |
| Hard PCIe Gen2 Blocks | Yes (2) |
| Package | 1152-BBGA, FCBGA (35 mm) |
| Process Technology | 40 nm low-power CMOS |
| Operating Temperature Grade | Commercial (0C to +85C) |
| Speed Grade | C4 |
| Mounting Type | Surface Mount (BGA) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Development Tool | Quartus II (legacy) |
EP2AGX190FF35C4G 1152-bbga, fcbga (35 mm) Pin Configuration Guide
Pin configuration for EP2AGX190FF35C4G (1152-bbga, fcbga (35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX190FF35C4G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX190FF35C4G is suitable for 7 applications: PCI Express Endpoint Card, Wireless Baseband Processing, Video Broadcasting Infrastructure, 10 Gigabit Ethernet Aggregation Switch, High-Speed Data Acquisition System, Industrial Protocol Bridge / Gateway, Aerospace / Defense Signal Processing.
PCI Express Endpoint Card
The EP2AGX190FF35C4G integrates two hard PCIe Gen2 IP blocks and 12 transceiver channels up to 6.375 Gbps, making it ideal for PCIe Gen2 x4 and x8 endpoint cards. Designers place the EP2AGX190 between a host PCIe slot and the user logic, leveraging the hard IP to skip the PCIe protocol stack implementation in soft logic. The 190K LEs provide ample capacity for endpoint DMA engines, scatter-gather controllers, and driver-state machines, while the 10 Mbit of embedded memory buffers high-throughput DMA payloads. The FCBGA1152 package is suitable for standard PCIe add-in card form factors with appropriate thermal relief.
Recommended
Wireless Baseband Processing
With 612 embedded 18x18 multipliers and 190K logic elements, the EP2AGX190FF35C4G delivers up to 600 GMACS of DSP throughput for wireless baseband processing in LTE, WiMAX, and proprietary OFDM systems. Designers implement uplink/downlink channel cards using the DSP blocks for FFT/iFFT, channel estimation, and MIMO detection, while the transceiver channels feed ADC data directly to FPGA SERDES inputs. The 10 Mbit of embedded memory holds channel state information and timing-critical look-up tables. The C4 speed grade provides comfortable timing margin for 200 MHz DSP datapaths, with Arria II GX architecture balancing DSP density against power consumption for thermally constrained outdoor baseband units.
Recommended
Video Broadcasting Infrastructure
The EP2AGX190FF35C4G supports SD/HD/3G-SDI serial digital video at rates up to 2.97 Gbps over its built-in transceivers, making it well suited to broadcast routers, format converters, and multiviewer products. With 12 transceivers, a single FPGA can aggregate up to 12 SDI streams and perform real-time cross-point switching, scaling, and overlay insertion. The 190K LEs support video processing pipelines including color space conversion, frame-rate conversion, and audio embedding/de-embedding. The 10 Mbit embedded memory is sized for several video line buffers, while the FCBGA package enables dense board designs for broadcast equipment racks.
Recommended
10 Gigabit Ethernet Aggregation Switch
The EP2AGX190FF35C4G's 12 transceivers at 6.375 Gbps natively support XAUI (4x3.125 Gbps) and 10GBASE-R datapaths, enabling 10 Gigabit Ethernet aggregation switch line cards. The transceiver hard IP includes 8b/10b encoding, word alignment, and clock-data recovery, allowing designers to focus on packet classification, QoS, and forwarding logic. With 190K LEs and 10 Mbit embedded memory, the FPGA can implement up to 256K MAC address table entries with L2/L3 lookup. The FCBGA1152 package suits line-card designs with adequate thermal relief for typical 8-12 W power dissipation.
Recommended
High-Speed Data Acquisition System
The EP2AGX190FF35C4G serves as a digital backend for high-speed ADC/DAC cards where 12 transceiver channels capture ADC serialized LVDS outputs (e.g., 14-bit ADCs at 250+ MSPS use 2-4 serial lanes per channel). With 190K LEs, the FPGA can implement digital down-conversion, FIR filtering, and decimation stages before DMA into host memory. The 10 Mbit of embedded memory provides 8-16 sample-deep FIFO buffers per channel. The 612 DSP blocks accelerate FIR and CIC filters required in SDR, radar, and medical imaging acquisition chains. The FCBGA package and proper thermal design enable continuous full-rate operation.
Recommended
Industrial Protocol Bridge / Gateway
The EP2AGX190FF35C4G bridges multiple industrial protocols including PROFINET, EtherCAT, SERCOS III, and serial fieldbuses (RS-485, CAN) by combining transceiver-based Ethernet with multi-standard IO and soft-logic protocol stacks. With 190K LEs, the FPGA supports dual PROFINET IRT controllers plus an EtherCAT slave stack simultaneously. The 10 Mbit of embedded memory holds configuration, diagnostic, and process image buffers for industrial real-time networks. The C4 commercial temperature grade (0C to +85C) suits industrial control cabinet environments, while the FCBGA package provides the mechanical robustness required for industrial vibration and shock profiles.
Recommended
Aerospace / Defense Signal Processing
The EP2AGX190FF35C4G's combination of transceiver channels, DSP blocks, and large logic capacity makes it suitable for aerospace and defense applications including radar signal processing, electronic warfare, and avionics databuses. With MIL-STD-1553 and ARINC 429 protocol IP available for the family, designers implement multi-protocol avionics interfaces alongside DSP-intensive processing. The 12 transceivers support high-speed sensor links and chassis-to-chassis connectivity. Designers should verify availability of the industrial temperature grade variant (I-suffix) and request full aerospace compliance documentation at order entry.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX190FF35C4G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX260FF35C4G | EP2AGX125FF35C4G | EP2AGX190FF35C4N | EP2AGX190EF29C4G | XC6VLX195T-2FF1156C |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Xilinx (AMD) |
| Package | 1152-BBGA FCBGA (FF35) | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 780-BBGA FCBGA (EF29) - different | FF1156 FCBGA - same ball count class, not pin-compatible |
| Logic Elements | 181,165 (~190K) | ~244K (+29%) | ~124K (-35%) | ~190K (identical) | ~190K (identical) | ~199K cells (+5%) |
| Transceiver Channels | 12 (up to 6.375 Gbps) | 12 (6.375 Gbps) | 12 (6.375 Gbps) | 12 (6.375 Gbps) | 12 (6.375 Gbps) | 20 (6.5 Gbps) |
| Speed Grade | C4 (commercial) | C4 | C4 | C4 | C4 | -2 (commercial) |
| RoHS Compliance | Yes (lead-free) | Yes | Yes | No (lead-bearing) | Yes | Yes |
| Approximate Single-Unit Price (USD, as of 2026-09-08) | $2,850 | $3,250 | $1,950 | $2,700 | $2,800 | $2,500 |
Key Differentiators
- Higher logic density than the EP2AGX125 in the same FF35 package (vs EP2AGX125FF35C4G)
- Drop-in upgrade path to higher density without PCB redesign (vs EP2AGX260FF35C4G)
- Cost-effective vs. equivalent Xilinx Virtex-6 part (vs XC6VLX195T-2FF1156C)
- RoHS-compliant lead-free variant available (vs EP2AGX190FF35C4N)
Design Notes
Estimated: A 190K Arria II GX device at full transceiver utilization (12 channels at 6.375 Gbps) can dissipate 10-14 W; the FCBGA1152 FF35 package requires a minimum 4-layer PCB with continuous ground and power planes, plus a thermal relief pattern (15-20 vias in a 1.0 mm pitch grid) under the exposed die area. Without thermal relief, junction temperature can exceed 100C in still air. Always run Quartus II PowerPlay early in the design cycle to size the core and transceiver supplies correctly.
The FCBGA1152 package with 1.0 mm ball pitch demands an 8-layer PCB stackup minimum with microvia or stacked-via construction for inner-row breakout. Use 50 ohm controlled-impedance routing for all transceiver lanes with trace length matching to within 0.127 mm (5 mil) for each differential pair. Reference the Arria II GX Transceiver Layout Guidelines in the device handbook for via pattern, AC-coupling capacitor placement, and reference plane continuity.
The Arria II GX device requires multiple supply rails: core VCC (0.9V typical), VCCPD (3.0V), VCCIO (1.2-3.0V per bank), VCCR/VCCA_PLL (PLL supply), and VCCCH_GXB (1.5V transceiver). Power sequencing must satisfy the datasheet requirements - typically core before I/O. Use the Quartus PowerPlay analyzer with realistic toggle rates to size the decoupling network; a minimum of 24 x 100 nF and 8 x 10 uF ceramic capacitors is recommended near the package.
The Arria II GX uses legacy Quartus II (not Quartus Prime), with the last supported version being Quartus II 13.1. New designs targeting the latest toolchain should consider migration to Cyclone V or Arria 10. Also, the device has no on-chip flash for configuration; external EPCS or EPCQ configuration flash must be provisioned. JTAG chain integrity is critical - always include a JTAG header on the PCB for factory programming and board-level debug.
Transceiver channels at 6.375 Gbps require pre-emphasis and equalization settings tuned per channel; the Arria II GX has built-in adaptive equalization but manual tuning via the Transceiver Toolkit improves margin. AC-coupling capacitors (0.1 uF) must be placed within 4 inches of the receiver pins. Reference clock distribution to multiple transceiver channels requires a low-jitter clock buffer (e.g., CDCM61001) with rms jitter below 1 ps to meet bit-error-rate targets.
Compliance Information
G suffix confirms RoHS-compliant lead-free material set. AEC-Q100 not applicable for FPGAs. REACH compliance per Intel product declaration.