EPC1664PI8 - 16Mb Enhanced Config Device for Stratix/Cyclone | Altera
MPN: EPC1664PI8 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.85 | $128.50 |
| 100 | $11.2 | $1,120.00 |
| 500 | $9.95 | $4,975.00 |
| 1,000 | $8.75 | $8,750.00 |
EPC1664PI8 Overview
An Enhanced Configuration Device (EPC) is a member of the configuration-memory hierarchy used alongside PROMs, flash, and controller-based schemes. Conceptually it sits between generic serial PROMs (small bitstream storage) and full embedded memory controllers (large, multi-device solutions). EPC devices are purpose-built companions to Altera FPGAs, exposing a serial configuration interface that the FPGA masters at power-up. The EPC16 variant adds density, higher programming throughput, and cascade support relative to EPC4 and EPC8 predecessors.
Key features include 16,777,216 bits (16 Mb) of configuration storage, cascadable architecture that allows two EPC devices to be chained for larger FPGA bitstreams, and a low-pin-count serial interface that frees board space. The device operates over the industrial temperature range and supports in-system programming, allowing firmware upgrades without removing the FPGA from the board.
Technically, the EPC1664PI8 uses a 3.3 V supply and exposes a four-signal serial configuration bus (DATA, DCLK, nCONFIG, CONF_DONE plus JTAG). Programming algorithms are defined by the Altera Quartus II toolchain; the device appears as a JTAG-accessible target for boundary-scan and ISP. Read-back and verify operations are supported, simplifying board-level bring-up.
Typical applications include factory programming stations for Altera/Intel Stratix and Cyclone boards, production programming of FPGA-based industrial controllers, telecom line cards, and legacy FPGA-based designs where board rework is undesirable. The PDIP-8 form factor also supports through-hole prototype sockets and easy rework in engineering builds.
When designing in this part, ensure that the FPGA's MSEL pins select the EPC configuration mode, that nCONFIG and CONF_DONE are pulled correctly, and that the JTAG chain order matches the Quartus generated SOF/JIC file. Designers moving from 3.3 V to 1.8 V FPGAs should re-validate the level-shifter on the serial data path.
This page synthesizes distributor pricing for the EPC1664PI8, Altera (Intel) configuration device family cross-references, and practical design notes not consolidated in the original datasheet.
Drop-in alternatives for EPC1664PI8 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1664PI8 (same form factor and footprint) — differing in Package, Mounting Type, Configuration Interface, Operating Temperature, Memory Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC164C88N
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC144PI8
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.25 / Unit
View Datasheet →EPC1441PI8
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.25 / Unit
View Datasheet →EPC144PI8W
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPC1441PI8N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3.55 / Unit
View Datasheet →EPC1213PI8
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2.11 / Unit
View Datasheet →EPC1664PI8 Maximum Ratings & Electrical Characteristics
| Memory Density | 16 Mb (16,777,216 bits) |
| Device Family | Enhanced Configuration Device (EPC) |
| Supported FPGA Families | Stratix, Cyclone, APEX II, APEX 20K, Mercury, ACEX 1K |
| Configuration Interface | Serial (DATA, DCLK, nCONFIG, CONF_DONE) |
| Programming Interface | JTAG / ByteBlaster / MasterBlaster |
| Cascade Support | Yes - two EPC devices can be chained |
| In-System Programmable | Yes (ISP via JTAG) |
| Package | PDIP-8 (PI8) |
| Mounting Type | Through-Hole |
| Read-Back Support | Yes (verify/blank-check) |
EPC1664PI8 Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nCONFIG — Configuration control (active-low) |
| Pin 4 | GND — Ground |
| Pin 5 | CONF_DONE — Configuration complete status (open-drain) |
| Pin 6 | TDI — JTAG test data input |
| Pin 7 | TMS — JTAG test mode select |
| Pin 8 | VCC — Supply voltage (3.3 V typical) |
Typical Applications
EPC1664PI8 is suitable for 6 applications: Stratix FPGA Configuration Storage, Cyclone FPGA Factory Programming, Industrial Control Boards, Telecom Line Card Configuration, Legacy FPGA-Based Test Equipment, Prototype and Engineering Bring-Up.
Stratix FPGA Configuration Storage
The EPC1664PI8 stores up to 16 Mb of Stratix FPGA configuration bitstreams and is invoked by the FPGA at power-up via the serial configuration interface (DATA, DCLK, nCONFIG, CONF_DONE). With 16,777,216 bits of non-volatile storage it can hold complete Stratix EP1S series images without cascade, which simplifies board layout by eliminating a second configuration PROM. The JTAG in-system programming channel lets production engineers update bitstreams without removing the FPGA from the board, shortening manufacturing rework cycles. Verified Stratix compatibility from the Altera EPC16 datasheet makes the EPC1664PI8 a default choice for legacy Stratix boards where designers want a single-chip, through-hole configuration solution.
Recommended
Cyclone FPGA Factory Programming
On Cyclone-based production boards the EPC1664PI8 serves as the primary configuration PROM, with the Cyclone device mastering the serial read sequence at power-up. The 16 Mb density exceeds typical Cyclone EP1C bitstream sizes, leaving headroom for future firmware revisions without board rework. Cascade support allows two EPC1664PI8 devices to load larger Cyclone images when needed, while JTAG ISP via ByteBlaster or MasterBlaster supports field firmware upgrades. The PDIP-8 form factor suits bench programming fixtures and through-hole prototype sockets used during early bring-up. Source: Altera EPC16 datasheet confirms EPC16 family compatibility with Cyclone series.
Recommended
Industrial Control Boards
Industrial controller boards using APEX 20K, APEX 20KC, or APEX II FPGAs benefit from the EPC1664PI8's robust through-hole PDIP-8 package, which tolerates the mechanical and thermal stress of factory-floor environments better than fine-pitch surface-mount PROMs. The 16 Mb density fits full APEX 20K configuration images, while the JTAG interface enables secure field updates of PLC-style firmware with on-board verification. The Industrial operating temperature range and the ability to operate over extended supply-voltage conditions make the EPC1664PI8 well suited to legacy industrial controllers that still use these Altera FPGA families. Verified compatibility list in the EPC16 datasheet covers all three APEX 20K variants (20K, 20KC, 20KE).
Recommended
Telecom Line Card Configuration
Telecom line cards built on Altera APEX II and Mercury FPGAs use the EPC1664PI8 to retain the configuration bitstream through power-cycles, supporting fast system bring-up at line-card insertion. The 16 Mb density supports complete APEX II images, while the JTAG ISP channel allows carriers to push field updates and bug fixes without swapping hardware. The cascade feature allows two EPC1664PI8 devices to load larger Mercury bitstreams when needed. The non-volatile, in-system-programmable architecture aligns with carrier-grade requirements for remote firmware management. Source: Altera EPC16 datasheet confirms Mercury and APEX II support.
Recommended
Legacy FPGA-Based Test Equipment
Test and measurement equipment built on ACEX 1K and APEX 20K FPGAs uses the EPC1664PI8 to hold firmware that defines the instrument personality. The 16 Mb storage accommodates multi-image architectures where multiple test personalities are stored and swapped under host control via JTAG. The PDIP-8 through-hole package simplifies replacement on bench instruments where field-service technicians swap configuration PROMs during repair. Verified Altera documentation in the EPC16 datasheet (alldatasheet ref 560034) confirms ACEX 1K and APEX 20K compatibility for this use case.
Recommended
Prototype and Engineering Bring-Up
Engineering teams prototyping Stratix, Cyclone, APEX II, APEX 20K, Mercury, or ACEX 1K designs use the EPC1664PI8 in its PDIP-8 package as a friendly socketed solution during bring-up. The 16 Mb density is large enough to fit complete production bitstreams, allowing the prototype to mirror the eventual production hardware. JTAG ISP lets engineers iterate quickly on firmware without removing the device from the socket. Cascade support accommodates larger experimental bitstreams, and the Altera Quartus II toolchain automatically generates the correct JIC programming files. Verified configuration compatibility is documented in the EPC16 datasheet.
Recommended
Recommended Products Summary
Engineering reference data for EPC1664PI8 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC164C88N | EPC144PI8 | EPC1441PI8 | EPC144PI8W | EPC1441PI8N | EPC1213PI8 |
|---|---|---|---|---|---|---|---|
| Package | PDIP-8 (PI8) | PDIP-8 (PI8) - same | PDIP-8 (PI8) - same | PDIP-8 (PI8) - same | PDIP-8 (PI8) - same | PDIP-8 (PI8) - same | PDIP-8 (PI8) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Memory Density | 16 Mb | Lower than 16 Mb | Lower than 16 Mb | Lower than 16 Mb | Lower than 16 Mb | Lower than 16 Mb | Lower than 16 Mb |
| Configuration Interface | Serial (DATA/DCLK/nCONFIG/CONF_DONE) | Serial (same protocol) | Serial (same protocol) | Serial (same protocol) | Serial (same protocol) | Serial (same protocol) | Serial (same protocol) |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Cascade Support | Yes (2-device cascade to 32 Mb) | Yes | Yes | Yes | Yes | Yes | Yes |
| Mounting Type | Through-Hole (PDIP) | Through-Hole | Through-Hole | Through-Hole | Through-Hole | Through-Hole | Through-Hole |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest-density PDIP-8 EPC member (vs EPC144PI8 / EPC1441PI8)
- Through-hole PDIP-8 form factor (vs EPCQ16A (modern replacement))
- Single-vendor, single-toolchain support (vs Cross-brand serial PROMs)
Design Notes
Do not substitute a smaller-density EPC device for the EPC1664PI8 without verifying that the bitstream fits. Cascade two devices of the smaller density if needed, but ensure the FPGA's MSEL pins select cascade mode. The Altera EPC16 datasheet (alldatasheet ref 560034) shows the cascade wiring between CONF_DONE of device 1 and nCS of device 2.
Place the EPC1664PI8 within 100 mm of the FPGA's serial configuration pins to keep the DATA and DCLK traces short and matched. The 8-pin PDIP package simplifies layout on 2-layer prototypes; route JTAG signals (TCK, TMS, TDI, TDO) in a single daisy-chain with 10 kohm pull-ups on TCK, TMS, TDI to define the chain at power-up. Keep DCLK traces away from switching power inductors to avoid coupling noise into the configuration clock.
The EPC1664PI8 operates from a 3.3 V supply rail (verify exact VCC range in the EPC16 datasheet). Decouple VCC with a 100 nF ceramic capacitor placed within 5 mm of pin 8, plus a 10 uF bulk capacitor on the rail. The CONF_DONE pin is open-drain and requires a pull-up to VCC; do not drive it actively. During JTAG ISP, ensure the FPGA's VCCIO matches the EPC's VCC to avoid contention on shared JTAG lines.
Compliance Information
Compliance values not present in the verified web data; consult the original Altera EPC16 datasheet (36 pages, alldatasheet ref 560034) or the manufacturer product page for authoritative RoHS/REACH/lead-free declarations.
