EPC164C88N - Altera/Intel Configuration Device for SRAM FPGAs
MPN: EPC164C88N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.85 | $985.00 |
| 500 | $8.45 | $4,225.00 |
| 1,000 | $7.2 | $7,200.00 |
EPC164C88N Overview
A configuration PROM is a non-volatile memory specifically optimized to deliver the FPGA configuration bitstream to the SRAM-based configuration cells of an FPGA at power-up. These devices sit in the broader hierarchy of memory ICs (non-volatile memory -> PROM/EPROM/Flash -> configuration memory) and are designed for one-time or in-system reprogrammable FPGA configuration rather than general-purpose data storage. Unlike a generic SPI flash, an EPC device implements the Altera-specific configuration controller (passive serial, fast passive parallel, or FPP modes) so that no external host processor is required to load the FPGA. This category is sometimes referred to as an FPGA boot PROM, configuration PROM, or configuration bitstream memory.
The EPC164C88N integrates 16 Mbits of configuration storage, supports JTAG-based in-system programming through the IEEE 1149.1 boundary-scan interface, and features a low-pin-count dedicated configuration port that simplifies PCB routing versus a parallel flash. The UBGA-88 footprint is a thermally enhanced substrate that supports industrial operating temperatures, making the device suitable for production volumes where factory programming is preferred. Designers can reconfigure the device on the bench without removing it from the board, which shortens development cycles for FPGA prototype spins.
In a typical design, the EPC164C88N connects to the FPGA's configuration pins (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) and is selected by an external mode jumper or resistor on MSEL pins. At power-up, the FPGA drives nSTATUS low, the EPC clocks out the bitstream on DATA synchronized to DCLK, and the FPGA asserts CONF_DONE once loading is complete. The entire transaction is transparent to the application processor and is governed by Altera's configuration protocol rather than by user software, which simplifies BOM and reduces firmware complexity.
Common applications include factory-loaded configuration for Cyclone III development boards, industrial controllers built around Stratix III logic, and long-life-cycle industrial products where supply-chain traceability requires a single-source configuration IC from Intel. When designing with this part, ensure that the MSEL[2..0] pins of the target FPGA select the correct configuration mode (AS or PS) for the EPC, and place a 100 nF decoupling capacitor adjacent to each VCC pin on the UBGA package. Designers should also confirm the supported FPGA voltage mode (3.3V or 1.8V) before mixing EPC164C88N with newer low-voltage FPGA families.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EPC164C88N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC164C88N (same form factor and footprint) β differing in Package, Programming Interface, Mounting Type, Memory Density, Configuration Interface.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC16UC88N
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPC164C88N Maximum Ratings & Electrical Characteristics
| Function | In-system programmable configuration PROM for SRAM-based FPGAs |
| Memory Density | 16 Mbit |
| Configuration Interface | Altera passive serial / fast passive parallel |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) |
| Operating Voltage (VCCINT) | 3.3 V typical |
| Supported FPGA Voltages | 1.8 V, 2.5 V, 3.3 V, 5.0 V |
| Package | 88-pin UBGA (Ultra FineLine BGA) 11x8 mm |
| Mounting Type | Surface Mount (BGA) |
| Compatible FPGA Families | Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix GX, Stratix II GX, HardCopy II |
| Configuration Mode | Passive Serial (PS), Fast Passive Parallel (FPP) |
| Reprogrammability | Yes (in-system via JTAG) |
EPC164C88N Pin Configuration
| Pin A1 | GND β Ground reference |
| Pin A2 | DCLK β Configuration clock output to FPGA |
| Pin A3 | DATA0 β Configuration data output bit 0 |
| Pin A4 | DATA1 β Configuration data output bit 1 (FPP mode) |
| Pin A5 | DATA2 β Configuration data output bit 2 (FPP mode) |
| Pin A6 | DATA3 β Configuration data output bit 3 (FPP mode) |
| Pin A7 | VCC β Core supply 3.3V |
| Pin A8 | GND β Ground reference |
| Pin B1 | TDI β JTAG test data input |
| Pin B2 | TMS β JTAG test mode select |
| Pin B3 | TCK β JTAG test clock |
| Pin B4 | TDO β JTAG test data output |
| Pin B5 | nCONFIG β Configuration control from FPGA |
| Pin B6 | nSTATUS β Configuration status to FPGA |
| Pin B7 | CONF_DONE β Configuration complete to FPGA |
| Pin B8 | VCC β Core supply 3.3V |
Typical Applications
EPC164C88N is suitable for 7 applications: Cyclone III FPGA Configuration, Stratix III Industrial Controller, Stratix II GX Communication Backplane, HardCopy II ASIC Companion, Legacy Cyclone II Embedded Board, Cyclone II Motor Control Drive, Stratix GX Wireless Baseband Card.
Cyclone III FPGA Configuration
The EPC164C88N stores the configuration bitstream for Altera Cyclone III FPGAs at power-up, eliminating the need for an external boot PROM or microcontroller. With 16 Mbits of density and passive serial mode, it accommodates Cyclone III bitstreams from EP3C5 through EP3C120 densities. Designers connect the EPC164C88N's DATA, DCLK, nCONFIG, nSTATUS, and CONF_DONE pins directly to the FPGA configuration bank; the device auto-clocks out the bitstream on power-up, asserting CONF_DONE when complete. The JTAG interface allows in-system reprogramming for firmware updates without removing the board from the chassis.
Recommended
Stratix III Industrial Controller
Industrial controller boards built around Stratix III FPGAs use the EPC164C88N as the production configuration source because the 88-UBGA industrial-grade package supports long-life-cycle deployments. The 16-Mbit density covers Stratix III bitstreams up to EP3SL150, and passive serial mode ensures deterministic power-up behavior required in safety-critical industrial systems. JTAG reprogramming via the IEEE 1149.1 interface allows field upgrades through a JTAG header on the chassis. The UBGA-11x8 footprint offers better thermal performance than QFP alternatives for high-temperature industrial enclosures.
Recommended
Stratix II GX Communication Backplane
Backplane line cards using Stratix II GX FPGAs leverage the EPC164C88N to provide non-volatile configuration with minimal board area. The 88-UBGA 11x8 mm package is denser than 100-pin PQFP alternatives, freeing PCB real estate for transceiver magnetics and high-speed SERDES routing. The fast passive parallel (FPP) configuration mode supported by this device family accelerates the Stratix II GX configuration time versus passive serial, reducing time-to-ready after power-up - critical for telecom backplane cards that must initialize within milliseconds. JTAG access supports remote bitstream updates over the backplane JTAG chain.
Recommended
HardCopy II ASIC Companion
HardCopy II structured ASIC designs that require FPGA prototyping use the EPC164C88N on the prototype board to load the Stratix II-equivalent prototype, while the production HardCopy II ships pre-programmed by the foundry. Engineers share a single configuration bitstream between the Stratix II prototype and HardCopy II production, simplifying firmware development. The EPC164C88N's 16-Mbit density comfortably covers HardCopy II bitstreams for moderate-complexity designs. The 88-UBGA package supports the production temperature range required for HardCopy II reference designs in telecom and networking equipment.
Recommended
Legacy Cyclone II Embedded Board
Long-life-cycle embedded boards built around the Cyclone II FPGA family continue to use the EPC164C88N for factory-loaded configuration, especially in medical imaging, military communications, and industrial automation equipment with 10-15 year deployment horizons. The NRND status of this part means new designs should migrate to EPCQ-series devices, but field-deployed systems benefit from the EPC164C88N's mature, well-characterized supply chain. JTAG in-system programming allows bitstream updates through a service-port connector, eliminating the need for board removal during firmware upgrades.
Recommended
Cyclone II Motor Control Drive
Industrial motor drives built on Cyclone II FPGAs rely on the EPC164C88N to store deterministic control-loop configuration bitstreams that must be ready within milliseconds of drive power-up. The 16-Mbit density fits Cyclone II EP2C8 through EP2C70 bitstreams comfortably, and the 3.3V VCCINT matches motor-drive auxiliary rails without level shifters. The passive serial configuration interface ensures the FPGA is configured before the inverter stage is enabled, preventing unsafe switching during the boot window. JTAG access supports in-field firmware updates for tuning control-loop parameters per motor load profile.
Recommended
Stratix GX Wireless Baseband Card
Wireless baseband cards built on Stratix GX FPGAs use the EPC164C88N to provide factory-loaded configuration for the DSP logic and SERDES transceivers. The fast passive parallel configuration mode reduces time-to-ready on this high-density FPGA, which is critical for cellular base stations that must boot within carrier-grade timing windows. The 88-UBGA 11x8 mm footprint fits beneath the FPGA's BGA shadow on multi-layer PCBs, simplifying layout. JTAG chain access allows remote firmware updates from the base station controller through the maintenance interface.
Recommended
Recommended Products Summary
Engineering reference data for EPC164C88N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC16UC88N |
|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) |
| Package | 88-UBGA (11x8 mm) | 88-UBGA (11x8 mm) - identical |
| Memory Density | 16 Mbit | 16 Mbit - identical |
| Configuration Interface | Passive Serial / Fast Passive Parallel | Passive Serial / Fast Passive Parallel - identical |
| Programming Interface | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG - identical |
| Compatible FPGA Families | Cyclone / Stratix / HardCopy II families | Cyclone / Stratix / HardCopy II families - identical |
| Operating Voltage | 3.3 V | 3.3 V - identical |
| Lifecycle Status | NRND | NRND - identical |
Key Differentiators
- Identical 16-Mbit density and 88-UBGA footprint as the closest same-family alternative (vs EPC16UC88N)
- Mature, well-characterized configuration PROM with extensive field deployment history (vs Newer EPCQ-series configuration PROMs)
- Native 3.3 V VCCINT compatible with motor-drive auxiliary rails without level shifters (vs 1.8 V EPCQ-L configuration PROMs)
Design Notes
Place a 100 nF decoupling capacitor adjacent to each VCC ball of the 88-UBGA package and a bulk 10 uF tantalum or ceramic capacitor on the main 3.3 V rail within 25 mm of the device. UBGA packages require via-in-pad or via-near-pad PCB design with 0.4 mm pitch drill rules per IPC-7351; use NSMD land pads with ENIG or OSP surface finish for reliable solder joint formation. Confirm the BGA ball pattern against the Altera Enhanced Configuration Devices datasheet ball-map diagram before tape-out.
Route the FPGA configuration signals (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) as short, impedance-controlled traces with a ground reference plane beneath. The DCLK trace should be length-matched within 25 mm of the FPGA's DCLK pin to avoid setup/hold violations during configuration; series-terminate with 33 ohm resistors if the trace exceeds 50 mm. Keep configuration traces away from switching power converter edges and high-speed SERDES lanes to prevent crosstalk-induced configuration errors during power-up.
Verify that MSEL[2..0] pins on the target FPGA select the configuration mode (Passive Serial AS or PS, or Fast Passive Parallel FPP) supported by EPC164C88N - mismatched MSEL settings cause configuration failures. Do not substitute EPC164C88N with EPCQ-series devices on existing PCBs because the EPCQ family uses 16-pin SOIC or similar smaller packages, requiring PCB rework. Confirm the temperature grade ('C' for commercial, 'I' for industrial) matches the deployment environment - the wrong grade causes out-of-spec behavior at temperature extremes.
Compliance Information
Compliance data not present in the verified web data; lifecycle is NRND per distributor listings. RoHS, REACH, lead-free, and halogen-free status require verification against the manufacturer's product page or certificate of compliance.
