EPC16QC100II - 16Mb FPGA Configuration PROM, 100-PQFP | Altera (Intel)
MPN: EPC16QC100II β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.75 | $10,750.00 |
EPC16QC100II Overview
An FPGA configuration PROM is a specialized non-volatile memory device that holds the bitstream required to configure an SRAM-based FPGA at power-up. Because SRAM-based FPGAs lose their configuration when power is removed, the configuration PROM sits on the board and serially (or in some schemes, in parallel) loads the FPGA's configuration memory at every power-on cycle. EPC configuration PROMs sit at the bottom of the configuration-device hierarchy: configuration PROM -> serial configuration memory -> non-volatile boot memory -> FPGA configuration subsystem -> programmable logic device.
Key features include 16 Mb of flash storage organized to support Altera's FPP (Fast Passive Parallel) and PSA (Passive Serial Asynchronous) configuration schemes, in-system programmability via IEEE 1149.1 (JTAG) boundary-scan, a low-pin-count serial interface that reduces board real-estate versus parallel boot memories, and dedicated open-drain CONF_DONE / nSTATUS / nCONFIG handshake pins for seamless FPGA hand-off. The "II" suffix denotes the industrial-grade temperature variant.
The EPC16QC100II uses a 3.3 V core supply with 5 V tolerant I/O on configuration pins, supporting cascading of multiple PROMs to address FPGAs whose bitstream exceeds 16 Mb. Internally, the device implements a state machine that handles JTAG ISP (In-System Programming) and orchestrates the serial clock and data handshake required by the target FPGA. Compared to early EPC1/EPC2 PROMs, the EPC16 adds compression support, reducing the on-board PROM silicon needed to load a given FPGA by approximately 30%.
Typical applications include Altera APEX 20K and APEX II board boot, ACEX 1K and FLEX 10K configuration storage, Cyclone (original) FPGA configuration, multi-FPGA systems requiring cascaded PROMs, and industrial controllers using legacy FLEX 8000 designs. The part is also a common reference design point in educational FPGA labs.
Designers should note that the EPC16QC100II has been superseded by newer Altera/Intel configuration devices such as the EPCQ and EPCQ-A families for current FPGA families; for new designs targeting Cyclone IV / Cyclone 10 / Arria / Stratix, engineers should select EPCQ16 or EPCQ-A16 instead. However, the EPC16 remains the supported configuration device for many legacy designs and continues to ship from authorized distributors.
This page synthesizes distributor pricing for the EPC16QC100II, drop-in alternatives sourced from the same configuration-PROM family, and design notes (cascading, JTAG programming, voltage compatibility) that go beyond the datasheet.
Drop-in alternatives for EPC16QC100II β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC16QC100II (same form factor and footprint) β differing in Package, Memory Type, Programmability, Configuration Interface, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC16QC100
β Drop-Inβ In Stock
$14.95 / Unit
View Datasheet βEPC16QC100DM
β Drop-Inβ In Stock
$15.85 / Unit
View Datasheet βEPC16QC100-TAAC80
β Drop-Inβ In Stock
$25.2 / Unit
View Datasheet βEPC16QC-100T
β Drop-Inβ In Stock
$14.5 / Unit
View Datasheet βEPC16Q100
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPC16C100T
β Drop-Inβ In Stock
$16.2 / Unit
View Datasheet βEPC16QC100II Maximum Ratings & Electrical Characteristics
| Memory Type | FPGA Configuration PROM (Flash-based) |
| Memory Density | 16 Mbit |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone |
| Configuration Mode | FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous) |
| Programmability | In-System Programmable via IEEE 1149.1 (JTAG) |
| Cascade Support | Yes (multi-PROM cascading supported) |
| Core Supply Voltage | 3.3 V |
| I/O Tolerance | 5 V tolerant configuration pins |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) |
| Package Dimensions | 20 mm x 14 mm, 0.5 mm pitch |
| Lead Finish | Matte Tin (lead-free) |
| Operating Temperature | -40C to +85C (Industrial) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Configuration Pins | DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE |
| Compression Support | Yes (reduces on-PROM footprint vs uncompressed bitstream) |
EPC16QC100II Pin Configuration
| Pin 1 | DATA[0] β Configuration data output bit 0 (to FPGA DATA0) |
| Pin 2 | DATA[1] β Configuration data output bit 1 (to FPGA DATA1) |
| Pin 3 | DATA[2] β Configuration data output bit 2 |
| Pin 4 | DATA[3] β Configuration data output bit 3 |
| Pin 5 | DATA[4] β Configuration data output bit 4 |
| Pin 6 | DATA[5] β Configuration data output bit 5 |
| Pin 7 | DATA[6] β Configuration data output bit 6 |
| Pin 8 | DATA[7] β Configuration data output bit 7 |
| Pin 9 | GND β Ground |
| Pin 10 | VCC β 3.3 V core supply |
| Pin 11 | nCONFIG β Configuration control (from FPGA, active low) |
| Pin 12 | nSTATUS β Status output to FPGA (active low) |
| Pin 13 | CONF_DONE β Configuration done flag (open-drain to FPGA) |
| Pin 14 | DCLK β Configuration clock from FPGA |
| Pin 15 | OE β Output enable (active high, from FPGA) |
| Pin 16 | nCASC β Cascade output (to next PROM's nCASC) |
| Pin 17 | nCS β Chip select (active low) |
| Pin 18 | TDI β JTAG test data in |
| Pin 19 | TDO β JTAG test data out |
| Pin 20 | TMS β JTAG test mode select |
| Pin 21 | TCK β JTAG test clock |
| Pin 22 | NC β Not connected (per datasheet) |
| Pin 23 | VCC β 3.3 V core supply |
| Pin 24 | GND β Ground |
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| Pin 100 | GND β Ground |
Typical Applications
EPC16QC100II is suitable for 7 applications: APEX 20K FPGA Board Configuration, ACEX 1K and FLEX 10K Configuration Storage, Cyclone (Original) FPGA Boot Memory, Multi-FPGA Cascade Configuration Systems, Legacy Industrial Control Boards, FPGA Design Education and Training Labs, Aerospace and Defense Legacy Avionics.
APEX 20K FPGA Board Configuration
The EPC16QC100II is the original configuration PROM shipped with Altera APEX 20K reference designs. Its 16 Mbit flash storage holds the complete APEX 20K bitstream for densities up to APEX 20K400 in PSA mode; APEX 20K600 and above require two EPC16 devices in cascade. The 100-pin PQFP package places it adjacent to the FPGA on legacy development boards such as the APEX 20K DSP development kit, and the JTAG (IEEE 1149.1) interface lets engineers reprogram the PROM in-system via Quartus Programmer during firmware iteration cycles. Industrial -40C to +85C rating matches the APEX 20K operating range, eliminating temperature-induced reconfiguration failures in factory-floor controllers.
Recommended
ACEX 1K and FLEX 10K Configuration Storage
ACEX 1K (EP1K10/30/50/100) and FLEX 10K (EPF10K10 through EPF10K100) devices configure over the PSA serial protocol, and the EPC16QC100II stores the entire bitstream for any device up to FLEX 10K100 in a single PROM. Because ACEX/FLEX 10K are widely deployed in industrial automation, the EPC16QC100II's industrial temperature range and 3.3 V core with 5 V tolerant I/O make it a direct drop-in for those board designs. Two EPC16 PROMs can be cascaded for FLEX 10K130A and above via the nCASC pin, providing 32 Mbit total boot storage.
Recommended
Cyclone (Original) FPGA Boot Memory
The original Altera Cyclone family (EP1C3, EP1C4, EP1C6, EP1C12, EP1C20) uses the EPC16QC100II as a configuration memory on early Cyclone reference boards. A single EPC16 holds the full bitstream for EP1C3 through EP1C12; EP1C20 may require compression or partial cascade. Quartus generates a .pof file that the EPC16QC100II accepts via JTAG. Designers porting legacy Cyclone designs should note that newer Cyclone IV/10 LP devices require the EPCQ16 (SOIC-16) - not drop-in compatible with the EPC16QC100II's 100-pin PQFP.
Recommended
Multi-FPGA Cascade Configuration Systems
For large logic designs exceeding one FPGA's configuration memory, the EPC16QC100II supports cascading via the nCASC pin and daisy-chained DATA outputs. A two-PROM cascade delivers 32 Mbit, sufficient to load APEX II EP2A70 and similar high-density devices; a four-PROM cascade reaches 64 Mbit. The PROM handshake signals nCONFIG, nSTATUS, and CONF_DONE are wired in parallel across the cascade, allowing each PROM to release its data segment in sequence under FPGA control. This cascade topology is common in telecom backplane designs using multiple APEX II devices.
Recommended
Legacy Industrial Control Boards
Many long-lifecycle industrial controllers built in the early 2000s - servo drives, programmable logic controllers, and CNC machine interfaces - still ship with Altera FLEX 10K or APEX 20K FPGAs loaded by an EPC16QC100II configuration PROM. The EPC16QC100II's 3.3 V core with 5 V tolerant configuration pins allows it to coexist with older 5 V logic on the same backplane. Because many of these industrial products have 10-20 year service lifetimes, distributors continue to stock the EPC16QC100II for field replacement and refurbishment.
Recommended
FPGA Design Education and Training Labs
University FPGA labs and training centers use the EPC16QC100II as the configuration memory on Altera APEX 20K and FLEX 10K development boards that have been donated or surplused from industrial customers. The 100-pin PQFP is large enough for student hand-soldering practice, and the JTAG (IEEE 1149.1) interface allows students to program the PROM directly from Quartus without a separate programmer. Industrial temperature rating means lab boards work consistently in air-conditioned or unconditioned classrooms.
Recommended
Aerospace and Defense Legacy Avionics
Long-life aerospace and defense programs that adopted Altera FLEX 10K and APEX 20K devices in the 1990s and early 2000s continue to procure the EPC16QC100II for flight-control and avionics subsystems. The industrial -40C to +85C temperature range covers cockpit and equipment-bay environments, and the mature datasheet/reliability record makes it acceptable for FAA-certified hardware baselines. New aerospace programs are migrating to radiation-tolerant FPGAs (e.g. Microsemi/RT ProASIC3) with their own boot memories, but legacy programs continue to depend on EPC16-class PROMs.
Recommended
Recommended Products Summary
Engineering reference data for EPC16QC100II β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC16QC100 | EPC16QC100DM | EPC16QC100-TAAC80 | EPC16QC-100T | EPC16Q100 | EPC16C100T |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 100-pin PQFP | 100-pin PQFP - same | 100-pin PQFP - same | 100-pin PQFP - same | 100-pin PQFP - same | 100-pin PQFP - same | 100-pin PQFP - same |
| Memory Density | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Core Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Configuration Mode | FPP / PSA | FPP / PSA | FPP / PSA | FPP / PSA | FPP / PSA | FPP / PSA | FPP / PSA |
| Cascade Support | Yes (nCASC) | Yes (nCASC) | Yes (nCASC) | Yes (nCASC) | Yes (nCASC) | Yes (nCASC) | Yes (nCASC) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
| RoHS Compliance | Yes (matte-tin lead finish) | Yes | Yes | Yes | Yes | Yes | Yes |
| JTAG ISP (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Industrial -40C to +85C operating range covers factory-floor and outdoor enclosures without thermal derating (vs EPC16QC100 (commercial 0C to +70C))
- Same die as EPC16QC100DM with full pin-to-pin compatibility, allowing drop-in upgrade to industrial temperature grade without PCB change (vs EPC16QC100DM)
- 5 V tolerant configuration pins enable coexistence with older 5 V logic on legacy backplanes (vs EPCQ16 (modern replacement, SOIC-16, 3.3 V only))
Design Notes
The 100-pin PQFP package has a 0.5 mm lead pitch and a 20 x 14 mm body. Route the 8-bit DATA bus and the DCLK / nCONFIG / nSTATUS / CONF_DONE / OE control lines on the top layer to minimize stub lengths; place 33 ohm series damping resistors on DCLK and DATA lines longer than 50 mm to suppress ringing into the FPGA configuration pins. Keep the PROM within 50 mm of the FPGA to satisfy setup/hold timing on the DCLK signal.
Decouple VCC (3.3 V) with a 100 nF ceramic capacitor placed within 5 mm of the EPC16QC100II VCC pin pair, plus a bulk 10 uF tantalum or aluminum-polymer capacitor on the same supply rail. During JTAG in-system programming the PROM current draw spikes briefly; ensure the 3.3 V regulator can source at least 150 mA peak to avoid voltage collapse and JTAG programming failure.
Daisy-chain the JTAG signals (TDI, TDO, TMS, TCK) through both the FPGA and the EPC16QC100II when the EPC16 is the configuration master, so that Quartus Programmer can address both devices on a single JTAG chain. Add a 4.7 kohm pull-up on nCONFIG and a 1 kohm pull-up on CONF_DONE to keep the FPGA in a defined reset state during PROM power-up. The nSTATUS pin is open-drain and requires an external pull-up.
Do not assume EPC16QC100II configuration files can be directly ported to EPCQ16 - the bitstream format and JTAG instruction set differ. Quartus must regenerate the .pof file with the target PROM explicitly selected. Also, do not exceed the maximum cascade depth of four EPC16 devices without checking the FPGA's nCASC timing budget; cascaded PROM delays can violate the FPGA's configuration clock period on large APEX II devices.
Compliance Information
RoHS compliant per Altera/Intel product page - matte-tin lead finish. AEC-Q100 not applicable (FPGA configuration PROM is not an automotive-qualified part; automotive customers must consult Intel for AEC-Q100 equivalents). Halogen-free status not explicitly stated in available data.
